From 4f2e2480a8c3a65da342f88ee3955d699d14b53f Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 6 Jun 2016 20:57:22 -0700 Subject: [PATCH] When exceptions occur in D-mode, set pc=0x808, not 0x800 Closes #43 --- rocket/src/main/scala/csr.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala index 4f8df9be..47c4a7e2 100644 --- a/rocket/src/main/scala/csr.scala +++ b/rocket/src/main/scala/csr.scala @@ -358,7 +358,8 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) val causeIsDebugBreak = insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) val trapToDebug = Bool(usingDebug) && (causeIsDebugInt || causeIsDebugBreak || reg_debug) val delegate = Bool(p(UseVM)) && reg_mstatus.prv < PRV.M && Mux(cause(xLen-1), reg_mideleg(cause_lsbs), reg_medeleg(cause_lsbs)) - val tvec = Mux(trapToDebug, UInt(0x800), Mux(delegate, reg_stvec.sextTo(vaddrBitsExtended), reg_mtvec)) + val debugTVec = Mux(reg_debug, UInt(0x808), UInt(0x800)) + val tvec = Mux(trapToDebug, debugTVec, Mux(delegate, reg_stvec.sextTo(vaddrBitsExtended), reg_mtvec)) val epc = Mux(csr_debug, reg_dpc, Mux(Bool(p(UseVM)) && !csr_addr_priv(1), reg_sepc, reg_mepc)) io.fatc := insn_sfence_vm io.evec := Mux(io.exception || csr_xcpt, tvec, epc)