riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Merge pull request #491 from ucb-bar/ahb-hready-high

Browse Source 
ahb: don't violate spec with SRAM fuzzing
This commit is contained in:
Wesley W. Terpstra
2016-12-15 02:50:15 +00:00
committed by GitHub
parent 1a0021b818 a5b8fc2317
commit 4d87d07343
2 changed files with 8 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/main/scala/uncore/ahb/SRAM.scala
View File

@@ -91,8 +91,13 @@ class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4
val muxdata = Vec((p_mask.toBools zip (p_wdata zip d_rdata)) val muxdata = Vec((p_mask.toBools zip (p_wdata zip d_rdata))
map { case (m, (p, r)) => Mux(d_bypass && m, p, r) }) map { case (m, (p, r)) => Mux(d_bypass && m, p, r) })
// Don't fuzz hready when not in data phase
val d_request = Reg(Bool(false))
when (in.hready) { d_request := Bool(false) }
when (a_request) { d_request := Bool(true) }
// Finally, the outputs // Finally, the outputs
in.hreadyout := LFSR16(Bool(true))(0) // Bool(true) in.hreadyout := !d_request || LFSR16(Bool(true))(0) // Bool(true)
in.hresp := AHBParameters.RESP_OKAY in.hresp := AHBParameters.RESP_OKAY
in.hrdata := Mux(in.hreadyout, muxdata.asUInt, UInt(0)) in.hrdata := Mux(in.hreadyout, muxdata.asUInt, UInt(0))
} }

4
src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
View File

@@ -31,7 +31,7 @@ class RRTestCombinational(val bits: Int, rvalid: Bool => Bool, wready: Bool => B
val wdata = UInt(INPUT, width = bits) val wdata = UInt(INPUT, width = bits)
} }
val reg = Reg(UInt(width = bits)) val reg = RegInit(UInt(0, width = bits))
val rvalid_s = rvalid(io.rready) val rvalid_s = rvalid(io.rready)
val wready_s = wready(io.wvalid) val wready_s = wready(io.wvalid)
@@ -87,7 +87,7 @@ class RRTestRequest(val bits: Int,
val (riready, rovalid, _) = rflow(io.rivalid, io.roready, UInt(0, width = 1)) val (riready, rovalid, _) = rflow(io.rivalid, io.roready, UInt(0, width = 1))
val (wiready, wovalid, wdata) = wflow(io.wivalid, io.woready, io.wdata) val (wiready, wovalid, wdata) = wflow(io.wivalid, io.woready, io.wdata)
val reg = Reg(UInt(width = bits)) val reg = RegInit(UInt(0, width = bits))
io.riready := riready io.riready := riready
io.rovalid := rovalid io.rovalid := rovalid