diff --git a/src/main/scala/uncore/ahb/SRAM.scala b/src/main/scala/uncore/ahb/SRAM.scala
index c173c973..6c60c52b 100644
--- a/src/main/scala/uncore/ahb/SRAM.scala
+++ b/src/main/scala/uncore/ahb/SRAM.scala
@@ -91,8 +91,13 @@ class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4
     val muxdata = Vec((p_mask.toBools zip (p_wdata zip d_rdata))
                       map { case (m, (p, r)) => Mux(d_bypass && m, p, r) })
 
+    // Don't fuzz hready when not in data phase
+    val d_request = Reg(Bool(false))
+    when (in.hready) { d_request := Bool(false) }
+    when (a_request)  { d_request := Bool(true) }
+
     // Finally, the outputs
-    in.hreadyout := LFSR16(Bool(true))(0) // Bool(true)
+    in.hreadyout := !d_request || LFSR16(Bool(true))(0) // Bool(true)
     in.hresp     := AHBParameters.RESP_OKAY
     in.hrdata    := Mux(in.hreadyout, muxdata.asUInt, UInt(0))
   }
diff --git a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
index fd527fcb..2564c0a7 100644
--- a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
+++ b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
@@ -31,7 +31,7 @@ class RRTestCombinational(val bits: Int, rvalid: Bool => Bool, wready: Bool => B
     val wdata  = UInt(INPUT, width = bits)
   }
 
-  val reg = Reg(UInt(width = bits))
+  val reg = RegInit(UInt(0, width = bits))
 
   val rvalid_s = rvalid(io.rready)
   val wready_s = wready(io.wvalid)
@@ -87,7 +87,7 @@ class RRTestRequest(val bits: Int,
 
   val (riready, rovalid, _)     = rflow(io.rivalid, io.roready, UInt(0, width = 1))
   val (wiready, wovalid, wdata) = wflow(io.wivalid, io.woready, io.wdata)
-  val reg = Reg(UInt(width = bits))
+  val reg = RegInit(UInt(0, width = bits))
 
   io.riready := riready
   io.rovalid := rovalid