From 9d50704b642e2908cce35d81fd2a9524282e2517 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 14 Dec 2016 14:53:54 -0800 Subject: [PATCH 1/2] ahb: don't violate spec with SRAM fuzzing --- src/main/scala/uncore/ahb/SRAM.scala | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/main/scala/uncore/ahb/SRAM.scala b/src/main/scala/uncore/ahb/SRAM.scala index c173c973..6c60c52b 100644 --- a/src/main/scala/uncore/ahb/SRAM.scala +++ b/src/main/scala/uncore/ahb/SRAM.scala @@ -91,8 +91,13 @@ class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4 val muxdata = Vec((p_mask.toBools zip (p_wdata zip d_rdata)) map { case (m, (p, r)) => Mux(d_bypass && m, p, r) }) + // Don't fuzz hready when not in data phase + val d_request = Reg(Bool(false)) + when (in.hready) { d_request := Bool(false) } + when (a_request) { d_request := Bool(true) } + // Finally, the outputs - in.hreadyout := LFSR16(Bool(true))(0) // Bool(true) + in.hreadyout := !d_request || LFSR16(Bool(true))(0) // Bool(true) in.hresp := AHBParameters.RESP_OKAY in.hrdata := Mux(in.hreadyout, muxdata.asUInt, UInt(0)) } From a5b8fc231707847b3543d7f51cdab1b96613c6ec Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 14 Dec 2016 15:38:08 -0800 Subject: [PATCH 2/2] RegisterRouterTest: start up with 0 in registers to make VIP testing easier --- src/main/scala/uncore/tilelink2/RegisterRouterTest.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala index fd527fcb..2564c0a7 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala @@ -31,7 +31,7 @@ class RRTestCombinational(val bits: Int, rvalid: Bool => Bool, wready: Bool => B val wdata = UInt(INPUT, width = bits) } - val reg = Reg(UInt(width = bits)) + val reg = RegInit(UInt(0, width = bits)) val rvalid_s = rvalid(io.rready) val wready_s = wready(io.wvalid) @@ -87,7 +87,7 @@ class RRTestRequest(val bits: Int, val (riready, rovalid, _) = rflow(io.rivalid, io.roready, UInt(0, width = 1)) val (wiready, wovalid, wdata) = wflow(io.wivalid, io.woready, io.wdata) - val reg = Reg(UInt(width = bits)) + val reg = RegInit(UInt(0, width = bits)) io.riready := riready io.rovalid := rovalid