added misaligned instruction check, cleaned up badvaddr handling
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@ -41,9 +41,8 @@ class ioDpathPCR extends Bundle()
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val exception = Bool('input);
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val cause = UFix(5, 'input);
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val badvaddr_wen = Bool('input);
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val badvaddr_sel = Bool('input);
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val pc = UFix(VADDR_BITS, 'input);
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val ldst_addr = UFix(VADDR_BITS, 'input);
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val badvaddr = UFix(VADDR_BITS, 'input);
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val eret = Bool('input);
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}
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@ -99,7 +98,7 @@ class rocketDpathPCR extends Component
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}
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when (io.badvaddr_wen) {
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reg_badvaddr <== Mux(io.badvaddr_sel, io.pc, io.ldst_addr);
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reg_badvaddr <== io.badvaddr;
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}
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when (io.exception && !reg_status_et) {
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@ -153,7 +152,7 @@ class rocketDpathPCR extends Component
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is (PCR_COUNT) { rdata <== Cat(Fill(w, reg_count(w-1)), reg_count); }
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is (PCR_COMPARE) { rdata <== Cat(Fill(w, reg_compare(w-1)), reg_compare); }
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is (PCR_CAUSE) { rdata <== Cat(Bits(0,w+27), reg_cause); }
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is (PCR_MEMSIZE) { rdata <== MEMSIZE; }
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is (PCR_MEMSIZE) { rdata <== Bits(MEMSIZE_PAGES, 64); }
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is (PCR_LOG) { rdata <== Cat(Bits(0,63), reg_log_control); }
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is (PCR_FROMHOST) { rdata <== Cat(Fill(w, reg_fromhost(w-1)), reg_fromhost); }
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is (PCR_TOHOST) { rdata <== Cat(Fill(w, reg_tohost(w-1)), reg_tohost); }
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