32 lines
1.0 KiB
Scala
32 lines
1.0 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.diplomacy
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import Chisel._
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import freechips.rocketchip.config.Parameters
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abstract class DiplomaticSRAM(
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address: AddressSet,
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beatBytes: Int,
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devName: Option[String])(implicit p: Parameters) extends LazyModule
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{
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val device = devName
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.map(new SimpleDevice(_, Seq("sifive,sram0")))
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.getOrElse(new MemoryDevice())
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val resources = device.reg("mem")
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def bigBits(x: BigInt, tail: List[Boolean] = Nil): List[Boolean] =
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if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)
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def mask: List[Boolean] = bigBits(address.mask >> log2Ceil(beatBytes))
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// Use single-ported memory with byte-write enable
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def makeSinglePortedByteWriteSeqMem(size: Int, lanes: Int = beatBytes, bits: Int = 8) = {
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// We require the address range to include an entire beat (for the write mask)
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val mem = SeqMem(size, Vec(lanes, Bits(width = bits)))
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devName.foreach(n => mem.suggestName(n.split("-").last))
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mem
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}
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}
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