89 lines
4.4 KiB
Scala
89 lines
4.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.unittest
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import Chisel._
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import freechips.rocketchip.amba.ahb._
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import freechips.rocketchip.amba.apb._
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem.{BaseSubsystemConfig}
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.tilelink._
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case object TestDurationMultiplier extends Field[Int]
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class WithTestDuration(x: Int) extends Config((site, here, up) => {
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case TestDurationMultiplier => x
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})
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class WithAMBAUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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val txns = 100 * site(TestDurationMultiplier)
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val timeout = 50000 * site(TestDurationMultiplier)
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Seq(
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Module(new AHBBridgeTest(true, txns=8*txns, timeout=timeout)),
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Module(new AHBNativeTest(true, txns=6*txns, timeout=timeout)),
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Module(new AHBNativeTest(false,txns=6*txns, timeout=timeout)),
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Module(new APBBridgeTest(true, txns=6*txns, timeout=timeout)),
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Module(new APBBridgeTest(false,txns=6*txns, timeout=timeout)),
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Module(new AXI4LiteFuzzRAMTest(txns=6*txns, timeout=timeout)),
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Module(new AXI4FullFuzzRAMTest(txns=3*txns, timeout=timeout)),
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Module(new AXI4BridgeTest( txns=3*txns, timeout=timeout)),
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Module(new AXI4XbarTest( txns=1*txns, timeout=timeout)),
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Module(new AXI4RAMAsyncCrossingTest(txns=3*txns, timeout=timeout))) }
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})
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class WithTLSimpleUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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val txns = 100 * site(TestDurationMultiplier)
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val timeout = 50000 * site(TestDurationMultiplier)
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Seq(
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Module(new TLRAMSimpleTest(1, txns=15*txns, timeout=timeout)),
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Module(new TLRAMSimpleTest(4, txns=15*txns, timeout=timeout)),
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Module(new TLRAMSimpleTest(16, txns=15*txns, timeout=timeout)),
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Module(new TLRAMZeroDelayTest(4, txns=15*txns, timeout=timeout)),
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Module(new TLFuzzRAMTest( txns= 3*txns, timeout=timeout)),
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Module(new TLRR0Test( txns= 3*txns, timeout=timeout)),
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Module(new TLRR1Test( txns= 3*txns, timeout=timeout)),
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Module(new TLRAMRationalCrossingTest(txns= 3*txns, timeout=timeout)),
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Module(new TLRAMAsyncCrossingTest( txns= 5*txns, timeout=timeout)),
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Module(new TLRAMAtomicAutomataTest( txns=10*txns, timeout=timeout)),
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Module(new TLRAMECCTest(8, 4, txns=15*txns, timeout=timeout)),
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Module(new TLRAMECCTest(4, 1, txns=15*txns, timeout=timeout)),
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Module(new TLRAMECCTest(1, 1, txns=15*txns, timeout=timeout)) ) }
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})
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class WithTLWidthUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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val txns = 100 * site(TestDurationMultiplier)
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val timeout = 50000 * site(TestDurationMultiplier)
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Seq(
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Module(new TLRAMFragmenterTest( 4, 256, txns= 5*txns, timeout=timeout)),
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Module(new TLRAMFragmenterTest(16, 64, txns=15*txns, timeout=timeout)),
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Module(new TLRAMFragmenterTest( 4, 16, txns=15*txns, timeout=timeout)),
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Module(new TLRAMWidthWidgetTest( 1, 1, txns= 1*txns, timeout=timeout)),
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Module(new TLRAMWidthWidgetTest( 4, 64, txns= 4*txns, timeout=timeout)),
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Module(new TLRAMWidthWidgetTest(64, 4, txns= 5*txns, timeout=timeout)) ) }
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})
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class WithTLXbarUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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val txns = 100 * site(TestDurationMultiplier)
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val timeout = 50000 * site(TestDurationMultiplier)
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Seq(
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Module(new TLRAMXbarTest(1, txns=5*txns, timeout=timeout)),
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Module(new TLRAMXbarTest(2, txns=5*txns, timeout=timeout)),
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Module(new TLRAMXbarTest(8, txns=5*txns, timeout=timeout)),
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Module(new TLMulticlientXbarTest(4,4, txns=2*txns, timeout=timeout)) ) }
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})
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class AMBAUnitTestConfig extends Config(new WithAMBAUnitTests ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
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class TLSimpleUnitTestConfig extends Config(new WithTLSimpleUnitTests ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
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class TLWidthUnitTestConfig extends Config(new WithTLWidthUnitTests ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
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class TLXbarUnitTestConfig extends Config(new WithTLXbarUnitTests ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
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