Merge branch 'param-refactor-tl'

src/main/scala/RocketChip.scala

@@ -23,27 +23,31 @@ case object NOutstandingMemReqsPerChannel extends Field[Int]
 /** Whether to use the slow backup memory port [VLSI] */
 case object UseBackupMemoryPort extends Field[Boolean]
 /** Function for building some kind of coherence manager agent */
-case object BuildL2CoherenceManager extends Field[() => CoherenceAgent]
+case object BuildL2CoherenceManager extends Field[Parameters => CoherenceAgent]
 /** Function for building some kind of tile connected to a reset signal */
-case object BuildTiles extends Field[Seq[(Bool) => Tile]]
+case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
 /** Start address of the "io" region in the memory map */
 case object ExternalIOStart extends Field[BigInt]
 
 /** Utility trait for quick access to some relevant parameters */
-trait TopLevelParameters extends UsesParameters {
-  val htifW = params(HTIFWidth)
-  val nTiles = params(NTiles)
-  val nMemChannels = params(NMemoryChannels)
-  val nBanksPerMemChannel = params(NBanksPerMemoryChannel)
-  val nBanks = nMemChannels*nBanksPerMemChannel
-  val lsb = params(BankIdLSB)
-  val nMemReqs = params(NOutstandingMemReqsPerChannel)
-  val mifAddrBits = params(MIFAddrBits)
-  val mifDataBeats = params(MIFDataBeats)
-  val scrAddrBits = log2Up(params(HTIFNSCR))
-  val pcrAddrBits = 12
-  val xLen = params(XLen)
-  require(lsb + log2Up(nBanks) < mifAddrBits)
+trait HasTopLevelParameters {
+  implicit val p: Parameters
+  lazy val nTiles = p(NTiles)
+  lazy val htifW = p(HtifKey).width
+  lazy val csrAddrBits = 12
+  lazy val nMemChannels = p(NMemoryChannels)
+  lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
+  lazy val nBanks = nMemChannels*nBanksPerMemChannel
+  lazy val lsb = p(BankIdLSB)
+  lazy val nMemReqs = p(NOutstandingMemReqsPerChannel)
+  lazy val mifAddrBits = p(MIFAddrBits)
+  lazy val mifDataBeats = p(MIFDataBeats)
+  lazy val xLen = p(XLen)
+  lazy val nSCR =  p(HtifKey).nSCR
+  lazy val scrAddrBits = log2Up(nSCR)
+  lazy val scrDataBits = 64
+  lazy val scrDataBytes = scrDataBits / 8
+  //require(lsb + log2Up(nBanks) < mifAddrBits)
 }
 
 class MemBackupCtrlIO extends Bundle {
@@ -54,28 +58,30 @@ class MemBackupCtrlIO extends Bundle {
 }
 
 /** Top-level io for the chip */
-class BasicTopIO extends Bundle {
-  val host = new HostIO
+class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
+    with HasTopLevelParameters {
+  val host = new HostIO(htifW)
   val mem_backup_ctrl = new MemBackupCtrlIO
 }
 
-class TopIO extends BasicTopIO {
+class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
   val mem = new MemIO
 }
 
-class MultiChannelTopIO extends BasicTopIO with TopLevelParameters {
-  val mem = Vec(new NASTIIO, nMemChannels)
-  val mmio = new NASTIIO
+class MultiChannelTopIO(implicit p: Parameters) extends BasicTopIO()(p) {
+  val mem = Vec(new NastiIO, nMemChannels)
+  val mmio = new NastiIO
 }
 
 /** Top-level module for the chip */
 //TODO: Remove this wrapper once multichannel DRAM controller is provided
-class Top extends Module with TopLevelParameters {
+class Top extends Module with HasTopLevelParameters {
+  implicit val p = params
   val io = new TopIO
-  if(!params(UseZscale)) {
+  if(!p(UseZscale)) {
     val temp = Module(new MultiChannelTop)
-    val arb = Module(new NASTIArbiter(nMemChannels))
-    val conv = Module(new MemIONASTIIOConverter(params(CacheBlockOffsetBits)))
+    val arb = Module(new NastiArbiter(nMemChannels))
+    val conv = Module(new MemIONastiIOConverter(p(CacheBlockOffsetBits)))
     arb.io.master <> temp.io.mem
     conv.io.nasti <> arb.io.slave
     io.mem.req_cmd <> Queue(conv.io.mem.req_cmd)
@@ -85,7 +91,7 @@ class Top extends Module with TopLevelParameters {
     io.host <> temp.io.host
 
     // tie off the mmio port
-    val errslave = Module(new NASTIErrorSlave)
+    val errslave = Module(new NastiErrorSlave)
     errslave.io <> temp.io.mmio
   } else {
     val temp = Module(new ZscaleTop)
@@ -93,23 +99,24 @@ class Top extends Module with TopLevelParameters {
   }
 }
 
-class MultiChannelTop extends Module with TopLevelParameters {
+class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLevelParameters {
   val io = new MultiChannelTopIO
 
   // Build an Uncore and a set of Tiles
-  val uncore = Module(new Uncore, {case TLId => "L1ToL2"})
-  val tileList = uncore.io.htif zip params(BuildTiles) map { case(hl, bt) => bt(hl.reset) }
+  val innerTLParams = p.alterPartial({case TLId => "L1toL2" })
+  val uncore = Module(new Uncore()(innerTLParams))
+  val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) }
 
   // Connect each tile to the HTIF
   uncore.io.htif.zip(tileList).zipWithIndex.foreach {
     case ((hl, tile), i) =>
       tile.io.host.id := UInt(i)
       tile.io.host.reset := Reg(next=Reg(next=hl.reset))
-      tile.io.host.pcr.req <> Queue(hl.pcr.req)
-      hl.pcr.resp <> Queue(tile.io.host.pcr.resp)
+      tile.io.host.csr.req <> Queue(hl.csr.req)
+      hl.csr.resp <> Queue(tile.io.host.csr.resp)
       hl.ipi_req <> Queue(tile.io.host.ipi_req)
       tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
-      hl.debug_stats_pcr := tile.io.host.debug_stats_pcr
+      hl.debug_stats_csr := tile.io.host.debug_stats_csr
   }
 
   // Connect the uncore to the tile memory ports, HostIO and MemIO
@@ -118,7 +125,7 @@ class MultiChannelTop extends Module with TopLevelParameters {
   io.host <> uncore.io.host
   io.mem <> uncore.io.mem
   io.mmio <> uncore.io.mmio
-  if(params(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
+  if(p(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
 }
 
 /** Wrapper around everything that isn't a Tile.
@@ -126,18 +133,18 @@ class MultiChannelTop extends Module with TopLevelParameters {
   * Usually this is clocked and/or place-and-routed separately from the Tiles.
   * Contains the Host-Target InterFace module (HTIF).
   */
-class Uncore extends Module with TopLevelParameters {
+class Uncore(implicit val p: Parameters) extends Module with HasTopLevelParameters {
   val io = new Bundle {
-    val host = new HostIO
-    val mem = Vec(new NASTIIO, nMemChannels)
+    val host = new HostIO(htifW)
+    val mem = Vec(new NastiIO, nMemChannels)
     val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
     val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
-    val htif = Vec(new HTIFIO, nTiles).flip
+    val htif = Vec(new HtifIO, nTiles).flip
     val mem_backup_ctrl = new MemBackupCtrlIO
-    val mmio = new NASTIIO
+    val mmio = new NastiIO
   }
 
-  val htif = Module(new HTIF(CSRs.mreset)) // One HTIF module per chip
+  val htif = Module(new Htif(CSRs.mreset)) // One HTIF module per chip
   val outmemsys = Module(new OuterMemorySystem) // NoC, LLC and SerDes
   outmemsys.io.incoherent := htif.io.cpu.map(_.reset)
   outmemsys.io.htif_uncached <> htif.io.mem
@@ -149,28 +156,27 @@ class Uncore extends Module with TopLevelParameters {
     io.htif(i).id := htif.io.cpu(i).id
     htif.io.cpu(i).ipi_req <> io.htif(i).ipi_req
     io.htif(i).ipi_rep <> htif.io.cpu(i).ipi_rep
-    htif.io.cpu(i).debug_stats_pcr <> io.htif(i).debug_stats_pcr
+    htif.io.cpu(i).debug_stats_csr <> io.htif(i).debug_stats_csr
 
-    val pcr_arb = Module(new SMIArbiter(2, 64, 12))
-    pcr_arb.io.in(0) <> htif.io.cpu(i).pcr
-    pcr_arb.io.in(1) <> outmemsys.io.pcr(i)
-    io.htif(i).pcr <> pcr_arb.io.out
+    val csr_arb = Module(new SMIArbiter(2, xLen, csrAddrBits))
+    csr_arb.io.in(0) <> htif.io.cpu(i).csr
+    csr_arb.io.in(1) <> outmemsys.io.csr(i)
+    io.htif(i).csr <> csr_arb.io.out
   }
 
   // Arbitrate SCR access between MMIO and HTIF
-  val scrArb = Module(new SMIArbiter(2, 64, scrAddrBits))
   val scrFile = Module(new SCRFile)
-
+  val scrArb = Module(new SMIArbiter(2, scrDataBits, scrAddrBits))
   scrArb.io.in(0) <> htif.io.scr
   scrArb.io.in(1) <> outmemsys.io.scr
   scrFile.io.smi <> scrArb.io.out
   // scrFile.io.scr <> (... your SCR connections ...)
 
   // Wire the htif to the memory port(s) and host interface
-  io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
+  io.host.debug_stats_csr := htif.io.host.debug_stats_csr
   io.mem <> outmemsys.io.mem
   io.mmio <> outmemsys.io.mmio
-  if(params(UseBackupMemoryPort)) {
+  if(p(UseBackupMemoryPort)) {
     outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en
     VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr,
       outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW)
@@ -183,18 +189,18 @@ class Uncore extends Module with TopLevelParameters {
 /** The whole outer memory hierarchy, including a NoC, some kind of coherence
   * manager agent, and a converter from TileLink to MemIO.
   */ 
-class OuterMemorySystem extends Module with TopLevelParameters {
+class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLevelParameters {
   val io = new Bundle {
     val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
     val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
     val htif_uncached = (new ClientUncachedTileLinkIO).flip
     val incoherent = Vec(Bool(), nTiles).asInput
-    val mem = Vec(new NASTIIO, nMemChannels)
+    val mem = Vec(new NastiIO, nMemChannels)
     val mem_backup = new MemSerializedIO(htifW)
     val mem_backup_en = Bool(INPUT)
-    val pcr = Vec(new SMIIO(xLen, pcrAddrBits), nTiles)
+    val csr = Vec(new SMIIO(xLen, csrAddrBits), nTiles)
     val scr = new SMIIO(xLen, scrAddrBits)
-    val mmio = new NASTIIO
+    val mmio = new NastiIO
   }
 
   // Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
@@ -211,7 +217,7 @@ class OuterMemorySystem extends Module with TopLevelParameters {
 
   // Create point(s) of coherence serialization
   val nManagers = nMemChannels * nBanksPerMemChannel
-  val managerEndpoints = List.fill(nManagers) { params(BuildL2CoherenceManager)()}
+  val managerEndpoints = List.fill(nManagers) { p(BuildL2CoherenceManager)(p)}
   managerEndpoints.foreach { _.incoherent := io.incoherent }
 
   // Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
@@ -220,27 +226,26 @@ class OuterMemorySystem extends Module with TopLevelParameters {
   l1tol2net.io.managers <> managerEndpoints.map(_.innerTL)
 
   // Create a converter between TileLinkIO and MemIO for each channel
-  val outerTLParams = params.alterPartial({ case TLId => "L2ToMC" })
+  val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
   val backendBuffering = TileLinkDepths(0,0,0,0,0)
 
-  val addrMap = params(NASTIAddrHashMap)
+  val addrMap = p(GlobalAddrMap)
+  val addrHashMap = new AddrHashMap(addrMap)
+  val nMasters = managerEndpoints.size + 1
+  val nSlaves = addrHashMap.nEntries
 
   println("Generated Address Map")
-  for ((name, base, size, _) <- addrMap.sortedEntries) {
+  for ((name, base, size, _) <- addrHashMap.sortedEntries) {
     println(f"\t$name%s $base%x - ${base + size - 1}%x")
   }
 
-  val interconnect = Module(new NASTITopInterconnect)
+  val interconnect = Module(new NastiTopInterconnect(nMasters, nSlaves, addrMap)(p))
 
   for ((bank, i) <- managerEndpoints.zipWithIndex) {
-    val factor = params(TLDataBits) / params(MIFDataBits)
-    val outermostTLParams = outerTLParams.alterPartial({
-      case TLDataBeats => params(MIFDataBeats)
-      case TLDataBits => params(MIFDataBits)
-    })
-    val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams)
-    val narrow = Module(new TileLinkIONarrower(factor))(outerTLParams)
-    val conv = Module(new NASTIIOTileLinkIOConverter)(outermostTLParams)
+    val outermostTLParams = p.alterPartial({case TLId => "Outermost"})
+    val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
+    val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
+    val conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams))
     unwrap.io.in <> bank.outerTL
     narrow.io.in <> unwrap.io.out
     conv.io.tl <> narrow.io.out
@@ -252,24 +257,24 @@ class OuterMemorySystem extends Module with TopLevelParameters {
 
   for (i <- 0 until nTiles) {
     val csrName = s"conf:csr$i"
-    val csrPort = addrMap(csrName).port
-    val conv = Module(new SMIIONASTIIOConverter(xLen, pcrAddrBits))
+    val csrPort = addrHashMap(csrName).port
+    val conv = Module(new SMIIONastiIOConverter(xLen, csrAddrBits))
     conv.io.nasti <> interconnect.io.slaves(csrPort)
-    io.pcr(i) <> conv.io.smi
+    io.csr(i) <> conv.io.smi
   }
 
-  val conv = Module(new SMIIONASTIIOConverter(xLen, scrAddrBits))
-  conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port)
+  val conv = Module(new SMIIONastiIOConverter(scrDataBits, scrAddrBits))
+  conv.io.nasti <> interconnect.io.slaves(addrHashMap("conf:scr").port)
   io.scr <> conv.io.smi
 
-  io.mmio <> interconnect.io.slaves(addrMap("io").port)
+  io.mmio <> interconnect.io.slaves(addrHashMap("io").port)
 
   val mem_channels = interconnect.io.slaves.take(nMemChannels)
 
   // Create a SerDes for backup memory port
-  if(params(UseBackupMemoryPort)) {
+  if(p(UseBackupMemoryPort)) {
     VLSIUtils.doOuterMemorySystemSerdes(
       mem_channels, io.mem, io.mem_backup, io.mem_backup_en,
-      nMemChannels, params(HTIFWidth), params(CacheBlockOffsetBits))
+      nMemChannels, htifW, p(CacheBlockOffsetBits))
   } else { io.mem <> mem_channels }
 }