diff --git a/junctions b/junctions index 70a5971a..5f099ddb 160000 --- a/junctions +++ b/junctions @@ -1 +1 @@ -Subproject commit 70a5971a223380f9334105aa715ba38fad9ef5f2 +Subproject commit 5f099ddb2186687d3e309e870676e63c8844e7e0 diff --git a/rocket b/rocket index ca266809..4d29d5c4 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit ca26680973158727c4c7dcbff0d3054b988d5f7a +Subproject commit 4d29d5c48cfaa3800bf5b6d5428a9c6e83335477 diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index 2f2044db..c0741726 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -15,25 +15,22 @@ class DefaultConfig extends ChiselConfig ( topDefinitions = { (pname,site,here) => type PF = PartialFunction[Any,Any] def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname) - def genCsrAddrMap() = { - val xLen = site(XLen) - val nSCR = site(HTIFNSCR) - val csrSize = (1 << 12) * (xLen / 8) - val nTiles = site(NTiles) - - (0 until nTiles) - .map(i => (s"csr$i", None, MemSize(csrSize, AddrMap.RW))) :+ - ("scr", None, MemSize(nSCR * xLen / 8, AddrMap.RW)) + def genCsrAddrMap: AddrMap = { + val csrSize = (1 << 12) * (site(XLen) / 8) + val csrs = (0 until site(NTiles)).map{ i => + AddrMapEntry(s"csr$i", None, MemSize(csrSize, AddrMapConsts.RW)) + } + val scrSize = site(HtifKey).nSCR * (site(XLen) / 8) + val scr = AddrMapEntry("scr", None, MemSize(scrSize, AddrMapConsts.RW)) + new AddrMap(csrs :+ scr) } pname match { - // case UseZscale => false - //HTIF Parameters - case HTIFWidth => Dump("HTIF_WIDTH", 16) - case HTIFNSCR => 64 - case HTIFSCRDataBits => site(XLen) - case HTIFOffsetBits => site(CacheBlockOffsetBits) - case HTIFNCores => site(NTiles) + case HtifKey => HtifParameters( + width = Dump("HTIF_WIDTH", 16), + nSCR = 64, + offsetBits = site(CacheBlockOffsetBits), + nCores = site(NTiles)) //Memory Parameters case PAddrBits => 32 case PgIdxBits => 12 @@ -50,9 +47,10 @@ class DefaultConfig extends ChiselConfig ( case MIFDataBits => Dump("MEM_DATA_BITS", 128) case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits)) case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits) - case NASTIDataBits => site(MIFDataBits) - case NASTIAddrBits => site(PAddrBits) - case NASTIIdBits => site(MIFTagBits) + case NastiKey => NastiParameters( + dataBits = site(MIFDataBits), + addrBits = site(PAddrBits), + idBits = site(MIFTagBits)) //Params used by all caches case NSets => findBy(CacheName) case NWays => findBy(CacheName) @@ -74,8 +72,7 @@ class DefaultConfig extends ChiselConfig ( case Replacer => () => new RandomReplacement(site(NWays)) case AmoAluOperandBits => site(XLen) //L1InstCache - case NBTBEntries => 62 - case NRAS => 2 + case BtbKey => BtbParameters() //L1DataCache case WordBits => site(XLen) case StoreDataQueueDepth => 17 @@ -86,15 +83,19 @@ class DefaultConfig extends ChiselConfig ( //L2 Memory System Params case NAcquireTransactors => 7 case L2StoreDataQueueDepth => 1 - case L2DirectoryRepresentation => new NullRepresentation(site(TLNCachingClients)) - case BuildL2CoherenceManager => () => - Module(new L2BroadcastHub, { case InnerTLId => "L1ToL2"; case OuterTLId => "L2ToMC" }) + case L2DirectoryRepresentation => new NullRepresentation(site(NTiles)) + case BuildL2CoherenceManager => (p: Parameters) => + Module(new L2BroadcastHub()(p.alterPartial({ + case InnerTLId => "L1toL2" + case OuterTLId => "L2toMC" }))) //Tile Constants case BuildTiles => { TestGeneration.addSuites(rv64i.map(_("p"))) TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rv64u.map(_(env)))) TestGeneration.addSuites(if(site(NTiles) > 1) List(mtBmarks, bmarks) else List(bmarks)) - List.fill(site(NTiles)){ (r:Bool) => Module(new RocketTile(resetSignal = r), {case TLId => "L1ToL2"}) } + List.fill(site(NTiles)){ (r: Bool, p: Parameters) => + Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1toL2"}))) + } } case BuildRoCC => None case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1) @@ -108,12 +109,11 @@ class DefaultConfig extends ChiselConfig ( case FastLoadByte => false case FastMulDiv => true case XLen => 64 - case NMultXpr => 32 case BuildFPU => { val env = if(site(UseVM)) List("p","pt","v") else List("p","pt") if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf)) else TestGeneration.addSuites(env.map(rv64ufNoDiv)) - Some(() => Module(new FPU)) + Some((p: Parameters) => Module(new FPU()(p))) } case FDivSqrt => true case SFMALatency => 2 @@ -124,41 +124,34 @@ class DefaultConfig extends ChiselConfig ( case NCustomMRWCSRs => 0 //Uncore Paramters case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock - case LNEndpoints => site(TLNManagers) + site(TLNClients) - case LNHeaderBits => log2Ceil(site(TLNManagers)) + log2Up(site(TLNClients)) - case TLBlockAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits) - case TLNClients => site(TLNCachingClients) + site(TLNCachelessClients) - case TLDataBits => site(CacheBlockBytes)*8/site(TLDataBeats) - case TLDataBeats => 4 - case TLWriteMaskBits => (site(TLDataBits) - 1) / 8 + 1 - case TLNetworkIsOrderedP2P => false - case TLNManagers => findBy(TLId) - case TLNCachingClients => findBy(TLId) - case TLNCachelessClients => findBy(TLId) - case TLCoherencePolicy => findBy(TLId) - case TLMaxManagerXacts => findBy(TLId) - case TLMaxClientXacts => findBy(TLId) - case TLMaxClientsPerPort => findBy(TLId) - case "L1ToL2" => { - case TLNManagers => site(NBanksPerMemoryChannel)*site(NMemoryChannels) - case TLNCachingClients => site(NTiles) - case TLNCachelessClients => site(NTiles) + 1 - case TLCoherencePolicy => new MESICoherence(site(L2DirectoryRepresentation)) - case TLMaxManagerXacts => site(NAcquireTransactors) + 2 - case TLMaxClientXacts => max(site(NMSHRs) + site(NIOMSHRs), - if(site(BuildRoCC).isEmpty) 1 - else site(RoCCMaxTaggedMemXacts)) - case TLMaxClientsPerPort => if(site(BuildRoCC).isEmpty) 1 else 3 - }:PF - case "L2ToMC" => { - case TLNManagers => 1 - case TLNCachingClients => site(NBanksPerMemoryChannel) - case TLNCachelessClients => 0 - case TLCoherencePolicy => new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))) - case TLMaxManagerXacts => 1 - case TLMaxClientXacts => 1 - case TLMaxClientsPerPort => site(NAcquireTransactors) + 2 - }:PF + case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients + case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) + + log2Up(site(TLKey(site(TLId))).nClients) + case TLKey("L1toL2") => + TileLinkParameters( + coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)), + nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels), + nCachingClients = site(NTiles), + nCachelessClients = site(NTiles) + 1, + maxClientXacts = max(site(NMSHRs) + site(NIOMSHRs), + if(site(BuildRoCC).isEmpty) 1 + else site(RoCCMaxTaggedMemXacts)), + maxClientsPerPort = if(site(BuildRoCC).isEmpty) 1 else 3, + maxManagerXacts = site(NAcquireTransactors) + 2, + addrBits = site(PAddrBits) - site(CacheBlockOffsetBits), + dataBits = site(CacheBlockBytes)*8)() + case TLKey("L2toMC") => + TileLinkParameters( + coherencePolicy = new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))), + nManagers = 1, + nCachingClients = site(NBanksPerMemoryChannel), + nCachelessClients = 0, + maxClientXacts = 1, + maxClientsPerPort = site(NAcquireTransactors) + 2, + maxManagerXacts = 1, + addrBits = site(PAddrBits) - site(CacheBlockOffsetBits), + dataBits = site(CacheBlockBytes)*8)() + case TLKey("Outermost") => site(TLKey("L2toMC")) case NTiles => Knob("NTILES") case NMemoryChannels => 1 case NBanksPerMemoryChannel => Knob("NBANKS") @@ -169,15 +162,10 @@ class DefaultConfig extends ChiselConfig ( case UseBackupMemoryPort => true case MMIOBase => BigInt(1 << 30) // 1 GB case ExternalIOStart => 2 * site(MMIOBase) - case NASTIAddrMap => Seq( - ("mem", None, MemSize(site(MMIOBase), AddrMap.RWX)), - ("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase), - genCsrAddrMap())), - ("io", Some(site(ExternalIOStart)), - MemSize(2 * site(MMIOBase), AddrMap.RW))) - case NASTIAddrHashMap => new AddrHashMap(site(NASTIAddrMap)) - case NASTINMasters => site(TLNManagers) + 1 - case NASTINSlaves => site(NASTIAddrHashMap).nEntries + case GlobalAddrMap => AddrMap( + AddrMapEntry("mem", None, MemSize(site(MMIOBase), AddrMapConsts.RWX)), + AddrMapEntry("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase), genCsrAddrMap)), + AddrMapEntry("io", Some(site(ExternalIOStart)), MemSize(2 * site(MMIOBase), AddrMapConsts.RW))) }}, knobValues = { case "NTILES" => 1 @@ -209,16 +197,16 @@ class WithL2Cache extends ChiselConfig( site(NBanksPerMemoryChannel)*site(NMemoryChannels)) / site(NWays) case NWays => Knob("L2_WAYS") - case RowBits => site(TLDataBits) + case RowBits => site(TLKey(site(TLId))).dataBits }: PartialFunction[Any,Any] case NAcquireTransactors => 2 case NSecondaryMisses => 4 - case L2DirectoryRepresentation => new FullRepresentation(site(TLNCachingClients)) - case BuildL2CoherenceManager => () => - Module(new L2HellaCacheBank, { + case L2DirectoryRepresentation => new FullRepresentation(site(NTiles)) + case BuildL2CoherenceManager => (p: Parameters) => + Module(new L2HellaCacheBank()(p.alterPartial({ case CacheName => "L2Bank" - case InnerTLId => "L1ToL2" - case OuterTLId => "L2ToMC"}) + case InnerTLId => "L1toL2" + case OuterTLId => "L2toMC"}))) }, knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048 } ) @@ -240,7 +228,7 @@ class WithZscale extends ChiselConfig( case BuildZscale => { TestGeneration.addSuites(List(rv32ui("p"), rv32um("p"))) TestGeneration.addSuites(List(zscaleBmarks)) - (r: Bool) => Module(new Zscale(r), {case TLId => "L1ToL2"}) + (r: Bool, p: Parameters) => Module(new Zscale(r)(p.alterPartial({case TLId => "L1toL2"}))) } case UseZscale => true case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024) @@ -264,7 +252,7 @@ class SmallConfig extends ChiselConfig ( case BuildFPU => None case FastMulDiv => false case NTLBEntries => 4 - case NBTBEntries => 8 + case BtbKey => BtbParameters(nEntries = 8) }}, knobValues = { case "L1D_SETS" => 64 diff --git a/src/main/scala/Network.scala b/src/main/scala/Network.scala index 03be1e3f..65f063ef 100644 --- a/src/main/scala/Network.scala +++ b/src/main/scala/Network.scala @@ -26,12 +26,13 @@ import uncore._ * each channel on the manager side of the network */ abstract class RocketChipNetwork( - addrToManagerId: UInt => UInt, - sharerToClientId: UInt => UInt, - clientDepths: TileLinkDepths, - managerDepths: TileLinkDepths) extends TLModule { - val nClients = params(TLNClients) - val nManagers = params(TLNManagers) + addrToManagerId: UInt => UInt, + sharerToClientId: UInt => UInt, + clientDepths: TileLinkDepths, + managerDepths: TileLinkDepths) + (implicit p: Parameters) extends TLModule()(p) { + val nClients = tlNClients + val nManagers = tlNManagers val io = new Bundle { val clients = Vec(new ClientTileLinkIO, nClients).flip val managers = Vec(new ManagerTileLinkIO, nManagers).flip @@ -39,21 +40,21 @@ abstract class RocketChipNetwork( val clients = io.clients.zipWithIndex.map { case (c, i) => { - val p = Module(new ClientTileLinkNetworkPort(i, addrToManagerId)) - val q = Module(new TileLinkEnqueuer(clientDepths)) - p.io.client <> c - q.io.client <> p.io.network - q.io.manager + val port = Module(new ClientTileLinkNetworkPort(i, addrToManagerId)) + val qs = Module(new TileLinkEnqueuer(clientDepths)) + port.io.client <> c + qs.io.client <> port.io.network + qs.io.manager } } val managers = io.managers.zipWithIndex.map { case (m, i) => { - val p = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId)) - val q = Module(new TileLinkEnqueuer(managerDepths)) - p.io.manager <> m - p.io.network <> q.io.manager - q.io.client + val port = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId)) + val qs = Module(new TileLinkEnqueuer(managerDepths)) + port.io.manager <> m + port.io.network <> qs.io.manager + qs.io.client } } } @@ -61,10 +62,11 @@ abstract class RocketChipNetwork( /** A simple arbiter for each channel that also deals with header-based routing. * Assumes a single manager agent. */ class RocketChipTileLinkArbiter( - sharerToClientId: UInt => UInt = (u: UInt) => u, - clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0), - managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0)) - extends RocketChipNetwork(u => UInt(0), sharerToClientId, clientDepths, managerDepths) + sharerToClientId: UInt => UInt = (u: UInt) => u, + clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0), + managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0)) + (implicit p: Parameters) + extends RocketChipNetwork(u => UInt(0), sharerToClientId, clientDepths, managerDepths)(p) with TileLinkArbiterLike with PassesId { val arbN = nClients @@ -86,13 +88,14 @@ class RocketChipTileLinkArbiter( * port id are done automatically. */ class RocketChipTileLinkCrossbar( - addrToManagerId: UInt => UInt = u => UInt(0), - sharerToClientId: UInt => UInt = u => u, - clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0), - managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0)) - extends RocketChipNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths) { - val n = params(LNEndpoints) - val count = params(TLDataBeats) + addrToManagerId: UInt => UInt = u => UInt(0), + sharerToClientId: UInt => UInt = u => u, + clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0), + managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0)) + (implicit p: Parameters) + extends RocketChipNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths)(p) { + val n = p(LNEndpoints) + val count = tlDataBeats // Actually instantiate the particular networks required for TileLink val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData()))) val relNet = Module(new BasicCrossbar(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData()))) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 92aec688..5eedc4a2 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -23,27 +23,31 @@ case object NOutstandingMemReqsPerChannel extends Field[Int] /** Whether to use the slow backup memory port [VLSI] */ case object UseBackupMemoryPort extends Field[Boolean] /** Function for building some kind of coherence manager agent */ -case object BuildL2CoherenceManager extends Field[() => CoherenceAgent] +case object BuildL2CoherenceManager extends Field[Parameters => CoherenceAgent] /** Function for building some kind of tile connected to a reset signal */ -case object BuildTiles extends Field[Seq[(Bool) => Tile]] +case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]] /** Start address of the "io" region in the memory map */ case object ExternalIOStart extends Field[BigInt] /** Utility trait for quick access to some relevant parameters */ -trait TopLevelParameters extends UsesParameters { - val htifW = params(HTIFWidth) - val nTiles = params(NTiles) - val nMemChannels = params(NMemoryChannels) - val nBanksPerMemChannel = params(NBanksPerMemoryChannel) - val nBanks = nMemChannels*nBanksPerMemChannel - val lsb = params(BankIdLSB) - val nMemReqs = params(NOutstandingMemReqsPerChannel) - val mifAddrBits = params(MIFAddrBits) - val mifDataBeats = params(MIFDataBeats) - val scrAddrBits = log2Up(params(HTIFNSCR)) - val pcrAddrBits = 12 - val xLen = params(XLen) - require(lsb + log2Up(nBanks) < mifAddrBits) +trait HasTopLevelParameters { + implicit val p: Parameters + lazy val nTiles = p(NTiles) + lazy val htifW = p(HtifKey).width + lazy val csrAddrBits = 12 + lazy val nMemChannels = p(NMemoryChannels) + lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel) + lazy val nBanks = nMemChannels*nBanksPerMemChannel + lazy val lsb = p(BankIdLSB) + lazy val nMemReqs = p(NOutstandingMemReqsPerChannel) + lazy val mifAddrBits = p(MIFAddrBits) + lazy val mifDataBeats = p(MIFDataBeats) + lazy val xLen = p(XLen) + lazy val nSCR = p(HtifKey).nSCR + lazy val scrAddrBits = log2Up(nSCR) + lazy val scrDataBits = 64 + lazy val scrDataBytes = scrDataBits / 8 + //require(lsb + log2Up(nBanks) < mifAddrBits) } class MemBackupCtrlIO extends Bundle { @@ -54,28 +58,30 @@ class MemBackupCtrlIO extends Bundle { } /** Top-level io for the chip */ -class BasicTopIO extends Bundle { - val host = new HostIO +class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p) + with HasTopLevelParameters { + val host = new HostIO(htifW) val mem_backup_ctrl = new MemBackupCtrlIO } -class TopIO extends BasicTopIO { +class TopIO(implicit p: Parameters) extends BasicTopIO()(p) { val mem = new MemIO } -class MultiChannelTopIO extends BasicTopIO with TopLevelParameters { - val mem = Vec(new NASTIIO, nMemChannels) - val mmio = new NASTIIO +class MultiChannelTopIO(implicit p: Parameters) extends BasicTopIO()(p) { + val mem = Vec(new NastiIO, nMemChannels) + val mmio = new NastiIO } /** Top-level module for the chip */ //TODO: Remove this wrapper once multichannel DRAM controller is provided -class Top extends Module with TopLevelParameters { +class Top extends Module with HasTopLevelParameters { + implicit val p = params val io = new TopIO - if(!params(UseZscale)) { + if(!p(UseZscale)) { val temp = Module(new MultiChannelTop) - val arb = Module(new NASTIArbiter(nMemChannels)) - val conv = Module(new MemIONASTIIOConverter(params(CacheBlockOffsetBits))) + val arb = Module(new NastiArbiter(nMemChannels)) + val conv = Module(new MemIONastiIOConverter(p(CacheBlockOffsetBits))) arb.io.master <> temp.io.mem conv.io.nasti <> arb.io.slave io.mem.req_cmd <> Queue(conv.io.mem.req_cmd) @@ -85,7 +91,7 @@ class Top extends Module with TopLevelParameters { io.host <> temp.io.host // tie off the mmio port - val errslave = Module(new NASTIErrorSlave) + val errslave = Module(new NastiErrorSlave) errslave.io <> temp.io.mmio } else { val temp = Module(new ZscaleTop) @@ -93,23 +99,24 @@ class Top extends Module with TopLevelParameters { } } -class MultiChannelTop extends Module with TopLevelParameters { +class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLevelParameters { val io = new MultiChannelTopIO // Build an Uncore and a set of Tiles - val uncore = Module(new Uncore, {case TLId => "L1ToL2"}) - val tileList = uncore.io.htif zip params(BuildTiles) map { case(hl, bt) => bt(hl.reset) } + val innerTLParams = p.alterPartial({case TLId => "L1toL2" }) + val uncore = Module(new Uncore()(innerTLParams)) + val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) } // Connect each tile to the HTIF uncore.io.htif.zip(tileList).zipWithIndex.foreach { case ((hl, tile), i) => tile.io.host.id := UInt(i) tile.io.host.reset := Reg(next=Reg(next=hl.reset)) - tile.io.host.pcr.req <> Queue(hl.pcr.req) - hl.pcr.resp <> Queue(tile.io.host.pcr.resp) + tile.io.host.csr.req <> Queue(hl.csr.req) + hl.csr.resp <> Queue(tile.io.host.csr.resp) hl.ipi_req <> Queue(tile.io.host.ipi_req) tile.io.host.ipi_rep <> Queue(hl.ipi_rep) - hl.debug_stats_pcr := tile.io.host.debug_stats_pcr + hl.debug_stats_csr := tile.io.host.debug_stats_csr } // Connect the uncore to the tile memory ports, HostIO and MemIO @@ -118,7 +125,7 @@ class MultiChannelTop extends Module with TopLevelParameters { io.host <> uncore.io.host io.mem <> uncore.io.mem io.mmio <> uncore.io.mmio - if(params(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl } + if(p(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl } } /** Wrapper around everything that isn't a Tile. @@ -126,18 +133,18 @@ class MultiChannelTop extends Module with TopLevelParameters { * Usually this is clocked and/or place-and-routed separately from the Tiles. * Contains the Host-Target InterFace module (HTIF). */ -class Uncore extends Module with TopLevelParameters { +class Uncore(implicit val p: Parameters) extends Module with HasTopLevelParameters { val io = new Bundle { - val host = new HostIO - val mem = Vec(new NASTIIO, nMemChannels) + val host = new HostIO(htifW) + val mem = Vec(new NastiIO, nMemChannels) val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip - val htif = Vec(new HTIFIO, nTiles).flip + val htif = Vec(new HtifIO, nTiles).flip val mem_backup_ctrl = new MemBackupCtrlIO - val mmio = new NASTIIO + val mmio = new NastiIO } - val htif = Module(new HTIF(CSRs.mreset)) // One HTIF module per chip + val htif = Module(new Htif(CSRs.mreset)) // One HTIF module per chip val outmemsys = Module(new OuterMemorySystem) // NoC, LLC and SerDes outmemsys.io.incoherent := htif.io.cpu.map(_.reset) outmemsys.io.htif_uncached <> htif.io.mem @@ -149,28 +156,27 @@ class Uncore extends Module with TopLevelParameters { io.htif(i).id := htif.io.cpu(i).id htif.io.cpu(i).ipi_req <> io.htif(i).ipi_req io.htif(i).ipi_rep <> htif.io.cpu(i).ipi_rep - htif.io.cpu(i).debug_stats_pcr <> io.htif(i).debug_stats_pcr + htif.io.cpu(i).debug_stats_csr <> io.htif(i).debug_stats_csr - val pcr_arb = Module(new SMIArbiter(2, 64, 12)) - pcr_arb.io.in(0) <> htif.io.cpu(i).pcr - pcr_arb.io.in(1) <> outmemsys.io.pcr(i) - io.htif(i).pcr <> pcr_arb.io.out + val csr_arb = Module(new SMIArbiter(2, xLen, csrAddrBits)) + csr_arb.io.in(0) <> htif.io.cpu(i).csr + csr_arb.io.in(1) <> outmemsys.io.csr(i) + io.htif(i).csr <> csr_arb.io.out } // Arbitrate SCR access between MMIO and HTIF - val scrArb = Module(new SMIArbiter(2, 64, scrAddrBits)) val scrFile = Module(new SCRFile) - + val scrArb = Module(new SMIArbiter(2, scrDataBits, scrAddrBits)) scrArb.io.in(0) <> htif.io.scr scrArb.io.in(1) <> outmemsys.io.scr scrFile.io.smi <> scrArb.io.out // scrFile.io.scr <> (... your SCR connections ...) // Wire the htif to the memory port(s) and host interface - io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr + io.host.debug_stats_csr := htif.io.host.debug_stats_csr io.mem <> outmemsys.io.mem io.mmio <> outmemsys.io.mmio - if(params(UseBackupMemoryPort)) { + if(p(UseBackupMemoryPort)) { outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr, outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW) @@ -183,18 +189,18 @@ class Uncore extends Module with TopLevelParameters { /** The whole outer memory hierarchy, including a NoC, some kind of coherence * manager agent, and a converter from TileLink to MemIO. */ -class OuterMemorySystem extends Module with TopLevelParameters { +class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLevelParameters { val io = new Bundle { val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip val htif_uncached = (new ClientUncachedTileLinkIO).flip val incoherent = Vec(Bool(), nTiles).asInput - val mem = Vec(new NASTIIO, nMemChannels) + val mem = Vec(new NastiIO, nMemChannels) val mem_backup = new MemSerializedIO(htifW) val mem_backup_en = Bool(INPUT) - val pcr = Vec(new SMIIO(xLen, pcrAddrBits), nTiles) + val csr = Vec(new SMIIO(xLen, csrAddrBits), nTiles) val scr = new SMIIO(xLen, scrAddrBits) - val mmio = new NASTIIO + val mmio = new NastiIO } // Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory @@ -211,7 +217,7 @@ class OuterMemorySystem extends Module with TopLevelParameters { // Create point(s) of coherence serialization val nManagers = nMemChannels * nBanksPerMemChannel - val managerEndpoints = List.fill(nManagers) { params(BuildL2CoherenceManager)()} + val managerEndpoints = List.fill(nManagers) { p(BuildL2CoherenceManager)(p)} managerEndpoints.foreach { _.incoherent := io.incoherent } // Wire the tiles and htif to the TileLink client ports of the L1toL2 network, @@ -220,27 +226,26 @@ class OuterMemorySystem extends Module with TopLevelParameters { l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) // Create a converter between TileLinkIO and MemIO for each channel - val outerTLParams = params.alterPartial({ case TLId => "L2ToMC" }) + val outerTLParams = p.alterPartial({ case TLId => "L2toMC" }) val backendBuffering = TileLinkDepths(0,0,0,0,0) - val addrMap = params(NASTIAddrHashMap) + val addrMap = p(GlobalAddrMap) + val addrHashMap = new AddrHashMap(addrMap) + val nMasters = managerEndpoints.size + 1 + val nSlaves = addrHashMap.nEntries println("Generated Address Map") - for ((name, base, size, _) <- addrMap.sortedEntries) { + for ((name, base, size, _) <- addrHashMap.sortedEntries) { println(f"\t$name%s $base%x - ${base + size - 1}%x") } - val interconnect = Module(new NASTITopInterconnect) + val interconnect = Module(new NastiTopInterconnect(nMasters, nSlaves, addrMap)(p)) for ((bank, i) <- managerEndpoints.zipWithIndex) { - val factor = params(TLDataBits) / params(MIFDataBits) - val outermostTLParams = outerTLParams.alterPartial({ - case TLDataBeats => params(MIFDataBeats) - case TLDataBits => params(MIFDataBits) - }) - val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams) - val narrow = Module(new TileLinkIONarrower(factor))(outerTLParams) - val conv = Module(new NASTIIOTileLinkIOConverter)(outermostTLParams) + val outermostTLParams = p.alterPartial({case TLId => "Outermost"}) + val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams)) + val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost")) + val conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams)) unwrap.io.in <> bank.outerTL narrow.io.in <> unwrap.io.out conv.io.tl <> narrow.io.out @@ -252,24 +257,24 @@ class OuterMemorySystem extends Module with TopLevelParameters { for (i <- 0 until nTiles) { val csrName = s"conf:csr$i" - val csrPort = addrMap(csrName).port - val conv = Module(new SMIIONASTIIOConverter(xLen, pcrAddrBits)) + val csrPort = addrHashMap(csrName).port + val conv = Module(new SMIIONastiIOConverter(xLen, csrAddrBits)) conv.io.nasti <> interconnect.io.slaves(csrPort) - io.pcr(i) <> conv.io.smi + io.csr(i) <> conv.io.smi } - val conv = Module(new SMIIONASTIIOConverter(xLen, scrAddrBits)) - conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port) + val conv = Module(new SMIIONastiIOConverter(scrDataBits, scrAddrBits)) + conv.io.nasti <> interconnect.io.slaves(addrHashMap("conf:scr").port) io.scr <> conv.io.smi - io.mmio <> interconnect.io.slaves(addrMap("io").port) + io.mmio <> interconnect.io.slaves(addrHashMap("io").port) val mem_channels = interconnect.io.slaves.take(nMemChannels) // Create a SerDes for backup memory port - if(params(UseBackupMemoryPort)) { + if(p(UseBackupMemoryPort)) { VLSIUtils.doOuterMemorySystemSerdes( mem_channels, io.mem, io.mem_backup, io.mem_backup_en, - nMemChannels, params(HTIFWidth), params(CacheBlockOffsetBits)) + nMemChannels, htifW, p(CacheBlockOffsetBits)) } else { io.mem <> mem_channels } } diff --git a/src/main/scala/Vlsi.scala b/src/main/scala/Vlsi.scala index 4ae391ec..174016bd 100644 --- a/src/main/scala/Vlsi.scala +++ b/src/main/scala/Vlsi.scala @@ -7,24 +7,26 @@ import junctions._ import uncore._ class MemDessert extends Module { - val io = new MemDesserIO(params(HTIFWidth)) - val x = Module(new MemDesser(params(HTIFWidth))) + implicit val p = params + val io = new MemDesserIO(p(HtifKey).width) + val x = Module(new MemDesser(p(HtifKey).width)) io.narrow <> x.io.narrow io.wide <> x.io.wide } object VLSIUtils { def doOuterMemorySystemSerdes( - llcs: Seq[NASTIIO], - mems: Seq[NASTIIO], + llcs: Seq[NastiIO], + mems: Seq[NastiIO], backup: MemSerializedIO, en: Bool, nMemChannels: Int, htifWidth: Int, - blockOffsetBits: Int) { + blockOffsetBits: Int) + (implicit p: Parameters) { - val arb = Module(new NASTIArbiter(nMemChannels)) - val conv = Module(new MemIONASTIIOConverter(blockOffsetBits)) + val arb = Module(new NastiArbiter(nMemChannels)) + val conv = Module(new MemIONastiIOConverter(blockOffsetBits)) val mem_serdes = Module(new MemSerdes(htifWidth)) conv.io.nasti <> arb.io.slave diff --git a/src/main/scala/ZscaleChip.scala b/src/main/scala/ZscaleChip.scala index bcb6f5a1..627d1483 100644 --- a/src/main/scala/ZscaleChip.scala +++ b/src/main/scala/ZscaleChip.scala @@ -9,22 +9,22 @@ import rocket._ import zscale._ case object UseZscale extends Field[Boolean] -case object BuildZscale extends Field[(Bool) => Zscale] +case object BuildZscale extends Field[(Bool, Parameters) => Zscale] case object BootROMCapacity extends Field[Int] case object DRAMCapacity extends Field[Int] -class ZscaleSystem extends Module { +class ZscaleSystem(implicit p: Parameters) extends Module { val io = new Bundle { - val host = new HTIFIO - val jtag = new HASTIMasterIO().flip - val bootmem = new HASTISlaveIO().flip - val dram = new HASTISlaveIO().flip - val spi = new HASTISlaveIO().flip - val led = new POCIIO - val corereset = new POCIIO + val host = new HtifIO + val jtag = new HastiMasterIO().flip + val bootmem = new HastiSlaveIO().flip + val dram = new HastiSlaveIO().flip + val spi = new HastiSlaveIO().flip + val led = new PociIO + val corereset = new PociIO } - val core = params(BuildZscale)(io.host.reset) + val core = p(BuildZscale)(io.host.reset, p) val bootmem_afn = (addr: UInt) => addr(31, 14) === UInt(0) @@ -36,11 +36,11 @@ class ZscaleSystem extends Module { val led_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(0) val corereset_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(1) - val xbar = Module(new HASTIXbar(3, Seq(bootmem_afn, sbus_afn))) - val sadapter = Module(new HASTISlaveToMaster) - val sbus = Module(new HASTIBus(Seq(dram_afn, spi_afn, pbus_afn))) - val padapter = Module(new HASTItoPOCIBridge) - val pbus = Module(new POCIBus(Seq(led_afn, corereset_afn))) + val xbar = Module(new HastiXbar(3, Seq(bootmem_afn, sbus_afn))) + val sadapter = Module(new HastiSlaveToMaster) + val sbus = Module(new HastiBus(Seq(dram_afn, spi_afn, pbus_afn))) + val padapter = Module(new HastiToPociBridge) + val pbus = Module(new PociBus(Seq(led_afn, corereset_afn))) core.io.host <> io.host xbar.io.masters(0) <> io.jtag @@ -60,14 +60,14 @@ class ZscaleSystem extends Module { io.corereset <> pbus.io.slaves(1) } -class ZscaleTop extends Module { +class ZscaleTop(implicit p: Parameters) extends Module { val io = new Bundle { - val host = new HTIFIO + val host = new HtifIO } val sys = Module(new ZscaleSystem) - val bootmem = Module(new HASTISRAM(params(BootROMCapacity)/4)) - val dram = Module(new HASTISRAM(params(DRAMCapacity)/4)) + val bootmem = Module(new HastiSRAM(p(BootROMCapacity)/4)) + val dram = Module(new HastiSRAM(p(DRAMCapacity)/4)) sys.io.host <> io.host bootmem.io <> sys.io.bootmem diff --git a/uncore b/uncore index 52e1e91c..b0eece1f 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 52e1e91c281a03cd7b2399a0a811ad124749c1c8 +Subproject commit b0eece1f613d4aafa3f9cf5470576ffb5110e856 diff --git a/zscale b/zscale index 461e7ee1..3338af40 160000 --- a/zscale +++ b/zscale @@ -1 +1 @@ -Subproject commit 461e7ee16bb15144e14c42855bf2ee23abd51806 +Subproject commit 3338af40491ccfe4b403761d755372c201003e39