Merge branch 'param-refactor-tl'
This commit is contained in:
Henry Cook
@ -15,25 +15,22 @@ class DefaultConfig extends ChiselConfig (
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topDefinitions = { (pname,site,here) =>
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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def genCsrAddrMap() = {
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val xLen = site(XLen)
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val nSCR = site(HTIFNSCR)
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val csrSize = (1 << 12) * (xLen / 8)
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val nTiles = site(NTiles)
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(0 until nTiles)
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.map(i => (s"csr$i", None, MemSize(csrSize, AddrMap.RW))) :+
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("scr", None, MemSize(nSCR * xLen / 8, AddrMap.RW))
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def genCsrAddrMap: AddrMap = {
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val csrSize = (1 << 12) * (site(XLen) / 8)
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val csrs = (0 until site(NTiles)).map{ i =>
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AddrMapEntry(s"csr$i", None, MemSize(csrSize, AddrMapConsts.RW))
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}
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val scrSize = site(HtifKey).nSCR * (site(XLen) / 8)
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val scr = AddrMapEntry("scr", None, MemSize(scrSize, AddrMapConsts.RW))
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new AddrMap(csrs :+ scr)
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}
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pname match {
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//
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case UseZscale => false
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//HTIF Parameters
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case HTIFWidth => Dump("HTIF_WIDTH", 16)
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case HTIFNSCR => 64
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case HTIFSCRDataBits => site(XLen)
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case HTIFOffsetBits => site(CacheBlockOffsetBits)
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case HTIFNCores => site(NTiles)
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case HtifKey => HtifParameters(
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width = Dump("HTIF_WIDTH", 16),
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nSCR = 64,
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offsetBits = site(CacheBlockOffsetBits),
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nCores = site(NTiles))
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//Memory Parameters
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case PAddrBits => 32
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case PgIdxBits => 12
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@ -50,9 +47,10 @@ class DefaultConfig extends ChiselConfig (
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case MIFDataBits => Dump("MEM_DATA_BITS", 128)
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case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
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case NASTIDataBits => site(MIFDataBits)
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case NASTIAddrBits => site(PAddrBits)
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case NASTIIdBits => site(MIFTagBits)
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case NastiKey => NastiParameters(
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dataBits = site(MIFDataBits),
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addrBits = site(PAddrBits),
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idBits = site(MIFTagBits))
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//Params used by all caches
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case NSets => findBy(CacheName)
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case NWays => findBy(CacheName)
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@ -74,8 +72,7 @@ class DefaultConfig extends ChiselConfig (
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case Replacer => () => new RandomReplacement(site(NWays))
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case AmoAluOperandBits => site(XLen)
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//L1InstCache
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case NBTBEntries => 62
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case NRAS => 2
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case BtbKey => BtbParameters()
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//L1DataCache
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case WordBits => site(XLen)
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case StoreDataQueueDepth => 17
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@ -86,15 +83,19 @@ class DefaultConfig extends ChiselConfig (
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//L2 Memory System Params
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case NAcquireTransactors => 7
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case L2StoreDataQueueDepth => 1
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case L2DirectoryRepresentation => new NullRepresentation(site(TLNCachingClients))
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case BuildL2CoherenceManager => () =>
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Module(new L2BroadcastHub, { case InnerTLId => "L1ToL2"; case OuterTLId => "L2ToMC" })
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case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (p: Parameters) =>
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Module(new L2BroadcastHub()(p.alterPartial({
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC" })))
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//Tile Constants
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case BuildTiles => {
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TestGeneration.addSuites(rv64i.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rv64u.map(_(env))))
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TestGeneration.addSuites(if(site(NTiles) > 1) List(mtBmarks, bmarks) else List(bmarks))
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List.fill(site(NTiles)){ (r:Bool) => Module(new RocketTile(resetSignal = r), {case TLId => "L1ToL2"}) }
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List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
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Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1toL2"})))
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}
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}
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case BuildRoCC => None
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case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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@ -108,12 +109,11 @@ class DefaultConfig extends ChiselConfig (
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case FastLoadByte => false
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case FastMulDiv => true
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case XLen => 64
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case NMultXpr => 32
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case BuildFPU => {
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val env = if(site(UseVM)) List("p","pt","v") else List("p","pt")
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if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf))
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else TestGeneration.addSuites(env.map(rv64ufNoDiv))
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Some(() => Module(new FPU))
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Some((p: Parameters) => Module(new FPU()(p)))
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}
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case FDivSqrt => true
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case SFMALatency => 2
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@ -124,41 +124,34 @@ class DefaultConfig extends ChiselConfig (
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case NCustomMRWCSRs => 0
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//Uncore Paramters
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case LNEndpoints => site(TLNManagers) + site(TLNClients)
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case LNHeaderBits => log2Ceil(site(TLNManagers)) + log2Up(site(TLNClients))
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case TLBlockAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case TLNClients => site(TLNCachingClients) + site(TLNCachelessClients)
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case TLDataBits => site(CacheBlockBytes)*8/site(TLDataBeats)
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case TLDataBeats => 4
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case TLWriteMaskBits => (site(TLDataBits) - 1) / 8 + 1
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case TLNetworkIsOrderedP2P => false
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case TLNManagers => findBy(TLId)
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case TLNCachingClients => findBy(TLId)
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case TLNCachelessClients => findBy(TLId)
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case TLCoherencePolicy => findBy(TLId)
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case TLMaxManagerXacts => findBy(TLId)
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case TLMaxClientXacts => findBy(TLId)
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case TLMaxClientsPerPort => findBy(TLId)
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case "L1ToL2" => {
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case TLNManagers => site(NBanksPerMemoryChannel)*site(NMemoryChannels)
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case TLNCachingClients => site(NTiles)
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case TLNCachelessClients => site(NTiles) + 1
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case TLCoherencePolicy => new MESICoherence(site(L2DirectoryRepresentation))
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case TLMaxManagerXacts => site(NAcquireTransactors) + 2
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case TLMaxClientXacts => max(site(NMSHRs) + site(NIOMSHRs),
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if(site(BuildRoCC).isEmpty) 1
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else site(RoCCMaxTaggedMemXacts))
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case TLMaxClientsPerPort => if(site(BuildRoCC).isEmpty) 1 else 3
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}:PF
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case "L2ToMC" => {
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case TLNManagers => 1
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case TLNCachingClients => site(NBanksPerMemoryChannel)
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case TLNCachelessClients => 0
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case TLCoherencePolicy => new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel)))
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case TLMaxManagerXacts => 1
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case TLMaxClientXacts => 1
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case TLMaxClientsPerPort => site(NAcquireTransactors) + 2
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}:PF
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case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
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case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
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log2Up(site(TLKey(site(TLId))).nClients)
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case TLKey("L1toL2") =>
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TileLinkParameters(
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coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
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nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels),
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nCachingClients = site(NTiles),
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nCachelessClients = site(NTiles) + 1,
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maxClientXacts = max(site(NMSHRs) + site(NIOMSHRs),
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if(site(BuildRoCC).isEmpty) 1
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else site(RoCCMaxTaggedMemXacts)),
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maxClientsPerPort = if(site(BuildRoCC).isEmpty) 1 else 3,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
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dataBits = site(CacheBlockBytes)*8)()
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case TLKey("L2toMC") =>
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TileLinkParameters(
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coherencePolicy = new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = 1,
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nCachingClients = site(NBanksPerMemoryChannel),
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nCachelessClients = 0,
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maxClientXacts = 1,
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maxClientsPerPort = site(NAcquireTransactors) + 2,
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maxManagerXacts = 1,
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addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
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dataBits = site(CacheBlockBytes)*8)()
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case TLKey("Outermost") => site(TLKey("L2toMC"))
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case NTiles => Knob("NTILES")
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case NMemoryChannels => 1
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case NBanksPerMemoryChannel => Knob("NBANKS")
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@ -169,15 +162,10 @@ class DefaultConfig extends ChiselConfig (
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case UseBackupMemoryPort => true
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case MMIOBase => BigInt(1 << 30) // 1 GB
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case ExternalIOStart => 2 * site(MMIOBase)
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case NASTIAddrMap => Seq(
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("mem", None, MemSize(site(MMIOBase), AddrMap.RWX)),
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("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase),
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genCsrAddrMap())),
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("io", Some(site(ExternalIOStart)),
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MemSize(2 * site(MMIOBase), AddrMap.RW)))
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case NASTIAddrHashMap => new AddrHashMap(site(NASTIAddrMap))
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case NASTINMasters => site(TLNManagers) + 1
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case NASTINSlaves => site(NASTIAddrHashMap).nEntries
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case GlobalAddrMap => AddrMap(
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AddrMapEntry("mem", None, MemSize(site(MMIOBase), AddrMapConsts.RWX)),
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AddrMapEntry("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase), genCsrAddrMap)),
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AddrMapEntry("io", Some(site(ExternalIOStart)), MemSize(2 * site(MMIOBase), AddrMapConsts.RW)))
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}},
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knobValues = {
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case "NTILES" => 1
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@ -209,16 +197,16 @@ class WithL2Cache extends ChiselConfig(
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site(NBanksPerMemoryChannel)*site(NMemoryChannels)) /
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site(NWays)
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case NWays => Knob("L2_WAYS")
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case RowBits => site(TLDataBits)
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case RowBits => site(TLKey(site(TLId))).dataBits
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}: PartialFunction[Any,Any]
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case NAcquireTransactors => 2
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case NSecondaryMisses => 4
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case L2DirectoryRepresentation => new FullRepresentation(site(TLNCachingClients))
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case BuildL2CoherenceManager => () =>
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Module(new L2HellaCacheBank, {
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case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (p: Parameters) =>
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Module(new L2HellaCacheBank()(p.alterPartial({
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case CacheName => "L2Bank"
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case InnerTLId => "L1ToL2"
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case OuterTLId => "L2ToMC"})
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC"})))
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},
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knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048 }
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)
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@ -240,7 +228,7 @@ class WithZscale extends ChiselConfig(
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case BuildZscale => {
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TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
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TestGeneration.addSuites(List(zscaleBmarks))
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(r: Bool) => Module(new Zscale(r), {case TLId => "L1ToL2"})
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(r: Bool, p: Parameters) => Module(new Zscale(r)(p.alterPartial({case TLId => "L1toL2"})))
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}
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case UseZscale => true
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case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)
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@ -264,7 +252,7 @@ class SmallConfig extends ChiselConfig (
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case BuildFPU => None
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case FastMulDiv => false
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case NTLBEntries => 4
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case NBTBEntries => 8
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case BtbKey => BtbParameters(nEntries = 8)
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}},
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knobValues = {
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case "L1D_SETS" => 64
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