riscv/rocket-chip
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fix TL width adapter and make it easier to switch inner data width

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This commit is contained in:
Howard Mao 2016-06-08 10:16:04 -07:00
parent a809a1712a
commit 40ab0a7960
2 changed files with 6 additions and 4 deletions
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8
src/main/scala/Configs.scala
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@ -105,6 +105,8 @@ class BaseConfig extends Config (
res append '\u0000'
res.toString.getBytes
}
lazy val innerDataBits = site(MIFDataBits)
lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
pname match {
case HtifKey => HtifParameters(
width = Dump("HTIF_WIDTH", 16),
@ -262,7 +264,7 @@ class BaseConfig extends Config (
if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBeats = site(MIFDataBeats),
dataBeats = innerDataBeats,
dataBits = site(CacheBlockBytes)*8)
case TLKey("L2toMC") =>
TileLinkParameters(
@ -274,7 +276,7 @@ class BaseConfig extends Config (
maxClientXacts = 1,
maxClientsPerPort = site(NAcquireTransactors) + 2,
maxManagerXacts = 1,
dataBeats = site(MIFDataBeats),
dataBeats = innerDataBeats,
dataBits = site(CacheBlockBytes)*8)
case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
maxClientXacts = site(NAcquireTransactors) + 2,
@ -290,7 +292,7 @@ class BaseConfig extends Config (
maxClientXacts = 4,
maxClientsPerPort = 1,
maxManagerXacts = 1,
dataBeats = site(MIFDataBeats),
dataBeats = innerDataBeats,
dataBits = site(CacheBlockBytes) * 8)
}
case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))

2
uncore

@ -1 +1 @@
Subproject commit 9298f4239ce9d94caf46fa09f997cdb8b2bfbf84
Subproject commit 2929d5384c54549d9af529643d2d4d61f9df626f