diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index c95200c2..2347a0b6 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -105,6 +105,8 @@ class BaseConfig extends Config (
       res append '\u0000'
       res.toString.getBytes
     }
+    lazy val innerDataBits = site(MIFDataBits)
+    lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
     pname match {
       case HtifKey => HtifParameters(
                        width = Dump("HTIF_WIDTH", 16),
@@ -262,7 +264,7 @@ class BaseConfig extends Config (
               if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
           maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
           maxManagerXacts = site(NAcquireTransactors) + 2,
-          dataBeats = site(MIFDataBeats),
+          dataBeats = innerDataBeats,
           dataBits = site(CacheBlockBytes)*8)
       case TLKey("L2toMC") => 
         TileLinkParameters(
@@ -274,7 +276,7 @@ class BaseConfig extends Config (
           maxClientXacts = 1,
           maxClientsPerPort = site(NAcquireTransactors) + 2,
           maxManagerXacts = 1,
-          dataBeats = site(MIFDataBeats),
+          dataBeats = innerDataBeats,
           dataBits = site(CacheBlockBytes)*8)
       case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
         maxClientXacts = site(NAcquireTransactors) + 2,
@@ -290,7 +292,7 @@ class BaseConfig extends Config (
           maxClientXacts = 4,
           maxClientsPerPort = 1,
           maxManagerXacts = 1,
-          dataBeats = site(MIFDataBeats),
+          dataBeats = innerDataBeats,
           dataBits = site(CacheBlockBytes) * 8)
       }
       case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
diff --git a/uncore b/uncore
index 9298f423..2929d538 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 9298f4239ce9d94caf46fa09f997cdb8b2bfbf84
+Subproject commit 2929d5384c54549d9af529643d2d4d61f9df626f