From 408107447c1376938471a512881d21a67d54d18c Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 18 Apr 2017 21:41:52 -0700 Subject: [PATCH] debug: DMI response should be busy, not zero, when there is an error. (#685) --- src/main/scala/rocketchip/DebugTransport.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocketchip/DebugTransport.scala b/src/main/scala/rocketchip/DebugTransport.scala index c1a8b015..349336f3 100644 --- a/src/main/scala/rocketchip/DebugTransport.scala +++ b/src/main/scala/rocketchip/DebugTransport.scala @@ -159,7 +159,7 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig) nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp != UInt(0))) busyResp.addr := UInt(0) - busyResp.resp := UInt(0) + busyResp.resp := -1.S(DMIConsts.dmiRespSize.W).asUInt // Generalizing busy to 'all-F' busyResp.data := UInt(0) nonbusyResp.addr := dmiReqReg.addr