riscv/rocket-chip
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Fixed error with icache/btb resp mask.

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This commit is contained in:
Christopher Celio 2014-11-03 01:13:22 -08:00
parent 08d2c13330
commit 3be3cd7731
2 changed files with 3 additions and 5 deletions
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5
rocket/src/main/scala/btb.scala
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@ -230,9 +230,8 @@ class BTB extends Module with BTBParameters {
if (params(FetchWidth) == 1) { if (params(FetchWidth) == 1) {
io.resp.bits.mask := UInt(1) io.resp.bits.mask := UInt(1)
} else { } else {
io.resp.bits.mask := Mux(io.resp.valid, Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1)), // note: btb_resp is clock gated, so the mask is only relevant for the io.resp.valid case
((UInt(1) << UInt(params(FetchWidth)))-UInt(1))) io.resp.bits.mask := Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1))
// val all_ones = UInt((1 << coreFetchWidth)-1)
} }
if (nBHT > 0) { if (nBHT > 0) {

3
rocket/src/main/scala/icache.scala
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@ -114,9 +114,8 @@ class Frontend extends FrontendModule
io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits) io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits)
} }
val all_ones = UInt((1 << coreFetchWidth)-1) val all_ones = UInt((1 << (coreFetchWidth+1))-1)
val msk_pc = if (coreFetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(coreFetchWidth) -1+2,2) val msk_pc = if (coreFetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(coreFetchWidth) -1+2,2)
// TODO what is the best way to handle the clock-gating of s2_btb_resp_bits?
io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc) io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc)
io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(coreInstBytes)-1,0) != UInt(0) io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(coreInstBytes)-1,0) != UInt(0)