From 3be3cd7731ec5bbc582d03545b8dfa45596ba1a8 Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Mon, 3 Nov 2014 01:13:22 -0800 Subject: [PATCH] Fixed error with icache/btb resp mask. --- rocket/src/main/scala/btb.scala | 5 ++--- rocket/src/main/scala/icache.scala | 3 +-- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala index c5e7636d..d0506601 100644 --- a/rocket/src/main/scala/btb.scala +++ b/rocket/src/main/scala/btb.scala @@ -230,9 +230,8 @@ class BTB extends Module with BTBParameters { if (params(FetchWidth) == 1) { io.resp.bits.mask := UInt(1) } else { - io.resp.bits.mask := Mux(io.resp.valid, Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1)), - ((UInt(1) << UInt(params(FetchWidth)))-UInt(1))) -// val all_ones = UInt((1 << coreFetchWidth)-1) + // note: btb_resp is clock gated, so the mask is only relevant for the io.resp.valid case + io.resp.bits.mask := Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1)) } if (nBHT > 0) { diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index c854760b..cdf21bca 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -114,9 +114,8 @@ class Frontend extends FrontendModule io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits) } - val all_ones = UInt((1 << coreFetchWidth)-1) + val all_ones = UInt((1 << (coreFetchWidth+1))-1) val msk_pc = if (coreFetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(coreFetchWidth) -1+2,2) - // TODO what is the best way to handle the clock-gating of s2_btb_resp_bits? io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc) io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(coreInstBytes)-1,0) != UInt(0)