riscv/rocket-chip
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Fixed error with icache/btb resp mask.

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This commit is contained in:
Christopher Celio
2014-11-03 01:13:22 -08:00
parent 08d2c13330
commit 3be3cd7731
2 changed files with 3 additions and 5 deletions
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5
rocket/src/main/scala/btb.scala
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@ -230,9 +230,8 @@ class BTB extends Module with BTBParameters {
if (params(FetchWidth) == 1) {
io.resp.bits.mask := UInt(1)
} else {
io.resp.bits.mask := Mux(io.resp.valid, Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1)),
((UInt(1) << UInt(params(FetchWidth)))-UInt(1)))
// val all_ones = UInt((1 << coreFetchWidth)-1)
// note: btb_resp is clock gated, so the mask is only relevant for the io.resp.valid case
io.resp.bits.mask := Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1))
}
if (nBHT > 0) {