riscv/rocket-chip
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Use buses, rather than crossbars, by default in TLInterconnect

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We should eventually parameterize this, of course.
This commit is contained in:
Andrew Waterman 2016-05-26 16:10:42 -07:00
parent b6d26e90f8
commit 391a9b9110
2 changed files with 25 additions and 10 deletions
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10
uncore/src/main/scala/interconnect.scala
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@ -110,11 +110,11 @@ class PortedTileLinkCrossbar(
val phyHdrWidth = log2Up(n) val phyHdrWidth = log2Up(n)
val count = tlDataBeats val count = tlDataBeats
// Actually instantiate the particular networks required for TileLink // Actually instantiate the particular networks required for TileLink
val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData()))) val acqNet = Module(new BasicBus(CrossbarConfig(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData()))))
val relNet = Module(new BasicCrossbar(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData()))) val relNet = Module(new BasicBus(CrossbarConfig(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData()))))
val prbNet = Module(new BasicCrossbar(n, new Probe)) val prbNet = Module(new BasicBus(CrossbarConfig(n, new Probe)))
val gntNet = Module(new BasicCrossbar(n, new Grant, count, Some((g: PhysicalNetworkIO[Grant]) => g.payload.hasMultibeatData()))) val gntNet = Module(new BasicBus(CrossbarConfig(n, new Grant, count, Some((g: PhysicalNetworkIO[Grant]) => g.payload.hasMultibeatData()))))
val ackNet = Module(new BasicCrossbar(n, new Finish)) val ackNet = Module(new BasicBus(CrossbarConfig(n, new Finish)))
// Aliases for the various network IO bundle types // Aliases for the various network IO bundle types
type PNIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]] type PNIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]

25
uncore/src/main/scala/network.scala
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@ -19,19 +19,34 @@ class PhysicalNetworkIO[T <: Data](n: Int, dType: T) extends Bundle {
} }
class BasicCrossbarIO[T <: Data](n: Int, dType: T) extends Bundle { class BasicCrossbarIO[T <: Data](n: Int, dType: T) extends Bundle {
val in = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType))).flip val in = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType))).flip
val out = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType))) val out = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType)))
} }
abstract class PhysicalNetwork extends Module abstract class PhysicalNetwork extends Module
class BasicCrossbar[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Option[PhysicalNetworkIO[T] => Bool] = None) extends PhysicalNetwork { case class CrossbarConfig[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Option[PhysicalNetworkIO[T] => Bool] = None)
val io = new BasicCrossbarIO(n, dType)
abstract class AbstractCrossbar[T <: Data](conf: CrossbarConfig[T]) extends PhysicalNetwork {
val io = new BasicCrossbarIO(conf.n, conf.dType)
}
class BasicBus[T <: Data](conf: CrossbarConfig[T]) extends AbstractCrossbar(conf) {
val arb = Module(new LockingRRArbiter(io.in(0).bits, conf.n, conf.count, conf.needsLock))
arb.io.in <> io.in
arb.io.out.ready := io.out(arb.io.out.bits.header.dst).ready
for ((out, i) <- io.out zipWithIndex) {
out.valid := arb.io.out.valid && arb.io.out.bits.header.dst === UInt(i)
out.bits := arb.io.out.bits
}
}
class BasicCrossbar[T <: Data](conf: CrossbarConfig[T]) extends AbstractCrossbar(conf) {
io.in.foreach { _.ready := Bool(false) } io.in.foreach { _.ready := Bool(false) }
io.out.zipWithIndex.map{ case (out, i) => { io.out.zipWithIndex.map{ case (out, i) => {
val rrarb = Module(new LockingRRArbiter(io.in(0).bits, n, count, needsLock)) val rrarb = Module(new LockingRRArbiter(io.in(0).bits, conf.n, conf.count, conf.needsLock))
(rrarb.io.in, io.in).zipped.map{ case (arb, in) => { (rrarb.io.in, io.in).zipped.map{ case (arb, in) => {
val destined = in.bits.header.dst === UInt(i) val destined = in.bits.header.dst === UInt(i)
arb.valid := in.valid && destined arb.valid := in.valid && destined