From 391a9b91100869b41e706c7a662c6a062e4528ce Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 26 May 2016 16:10:42 -0700 Subject: [PATCH] Use buses, rather than crossbars, by default in TLInterconnect We should eventually parameterize this, of course. --- uncore/src/main/scala/interconnect.scala | 10 +++++----- uncore/src/main/scala/network.scala | 25 +++++++++++++++++++----- 2 files changed, 25 insertions(+), 10 deletions(-) diff --git a/uncore/src/main/scala/interconnect.scala b/uncore/src/main/scala/interconnect.scala index 88791815..c9fdb478 100644 --- a/uncore/src/main/scala/interconnect.scala +++ b/uncore/src/main/scala/interconnect.scala @@ -110,11 +110,11 @@ class PortedTileLinkCrossbar( val phyHdrWidth = log2Up(n) val count = tlDataBeats // Actually instantiate the particular networks required for TileLink - val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData()))) - val relNet = Module(new BasicCrossbar(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData()))) - val prbNet = Module(new BasicCrossbar(n, new Probe)) - val gntNet = Module(new BasicCrossbar(n, new Grant, count, Some((g: PhysicalNetworkIO[Grant]) => g.payload.hasMultibeatData()))) - val ackNet = Module(new BasicCrossbar(n, new Finish)) + val acqNet = Module(new BasicBus(CrossbarConfig(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData())))) + val relNet = Module(new BasicBus(CrossbarConfig(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData())))) + val prbNet = Module(new BasicBus(CrossbarConfig(n, new Probe))) + val gntNet = Module(new BasicBus(CrossbarConfig(n, new Grant, count, Some((g: PhysicalNetworkIO[Grant]) => g.payload.hasMultibeatData())))) + val ackNet = Module(new BasicBus(CrossbarConfig(n, new Finish))) // Aliases for the various network IO bundle types type PNIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]] diff --git a/uncore/src/main/scala/network.scala b/uncore/src/main/scala/network.scala index 64eff1d3..88f1a1b6 100644 --- a/uncore/src/main/scala/network.scala +++ b/uncore/src/main/scala/network.scala @@ -19,19 +19,34 @@ class PhysicalNetworkIO[T <: Data](n: Int, dType: T) extends Bundle { } class BasicCrossbarIO[T <: Data](n: Int, dType: T) extends Bundle { - val in = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType))).flip - val out = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType))) + val in = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType))).flip + val out = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType))) } abstract class PhysicalNetwork extends Module -class BasicCrossbar[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Option[PhysicalNetworkIO[T] => Bool] = None) extends PhysicalNetwork { - val io = new BasicCrossbarIO(n, dType) +case class CrossbarConfig[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Option[PhysicalNetworkIO[T] => Bool] = None) +abstract class AbstractCrossbar[T <: Data](conf: CrossbarConfig[T]) extends PhysicalNetwork { + val io = new BasicCrossbarIO(conf.n, conf.dType) +} + +class BasicBus[T <: Data](conf: CrossbarConfig[T]) extends AbstractCrossbar(conf) { + val arb = Module(new LockingRRArbiter(io.in(0).bits, conf.n, conf.count, conf.needsLock)) + arb.io.in <> io.in + + arb.io.out.ready := io.out(arb.io.out.bits.header.dst).ready + for ((out, i) <- io.out zipWithIndex) { + out.valid := arb.io.out.valid && arb.io.out.bits.header.dst === UInt(i) + out.bits := arb.io.out.bits + } +} + +class BasicCrossbar[T <: Data](conf: CrossbarConfig[T]) extends AbstractCrossbar(conf) { io.in.foreach { _.ready := Bool(false) } io.out.zipWithIndex.map{ case (out, i) => { - val rrarb = Module(new LockingRRArbiter(io.in(0).bits, n, count, needsLock)) + val rrarb = Module(new LockingRRArbiter(io.in(0).bits, conf.n, conf.count, conf.needsLock)) (rrarb.io.in, io.in).zipped.map{ case (arb, in) => { val destined = in.bits.header.dst === UInt(i) arb.valid := in.valid && destined