diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index 247bd8c7..36650cf4 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -41,7 +41,7 @@ class ioDpathAll extends Bundle()
   val vec_ctrl = new ioCtrlDpathVec().flip()
   val vec_iface = new ioDpathVecInterface()
   val vec_imul_req = new io_imul_req
-  val vec_imul_resp = Bits(hwacha.Config.DEF_XLEN, INPUT)
+  val vec_imul_resp = Bits(hwacha.Constants.SZ_XLEN, INPUT)
 }
 
 class rocketDpath extends Component
diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala
index 7e778685..6a27a9bb 100644
--- a/rocket/src/main/scala/dpath_vec.scala
+++ b/rocket/src/main/scala/dpath_vec.scala
@@ -4,13 +4,13 @@ import Chisel._
 import Node._
 import Constants._
 import Instructions._
-import hwacha.Interface._
+import hwacha.Constants._
 
 class ioDpathVecInterface extends Bundle
 {
-  val vcmdq_bits = Bits(VCMD_SZ, OUTPUT)
-  val vximm1q_bits = Bits(VIMM_SZ, OUTPUT)
-  val vximm2q_bits = Bits(VSTRIDE_SZ, OUTPUT)
+  val vcmdq_bits = Bits(SZ_VCMD, OUTPUT)
+  val vximm1q_bits = Bits(SZ_VIMM, OUTPUT)
+  val vximm2q_bits = Bits(SZ_VSTRIDE, OUTPUT)
 }
 
 class ioDpathVec extends Bundle
diff --git a/rocket/src/main/scala/multiplier.scala b/rocket/src/main/scala/multiplier.scala
index cfe4658e..9e35dcc9 100644
--- a/rocket/src/main/scala/multiplier.scala
+++ b/rocket/src/main/scala/multiplier.scala
@@ -4,7 +4,7 @@ import Chisel._
 import Node._
 import Constants._
 import hwacha._
-import hwacha.Config._
+import hwacha.Constants._
 
 class ioMultiplier extends Bundle {
   val req = new io_imul_req().flip()
@@ -13,7 +13,7 @@ class ioMultiplier extends Bundle {
   val resp_val = Bool(OUTPUT)
   val resp_rdy = Bool(INPUT)
   val resp_tag = Bits(5, OUTPUT)
-  val resp_bits = Bits(DEF_XLEN, OUTPUT)
+  val resp_bits = Bits(SZ_XLEN, OUTPUT)
 }
 
 class rocketVUMultiplier(nwbq: Int) extends Component {
@@ -21,7 +21,7 @@ class rocketVUMultiplier(nwbq: Int) extends Component {
     val cpu = new ioMultiplier
     val vu = new Bundle {
       val req = new io_imul_req
-      val resp = Bits(DEF_XLEN, INPUT)
+      val resp = Bits(SZ_XLEN, INPUT)
     }
   }