diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala
index 06718f7e..31400589 100644
--- a/rocket/src/main/scala/htif.scala
+++ b/rocket/src/main/scala/htif.scala
@@ -27,7 +27,7 @@ class ioHTIF extends Bundle
   val reset = Bool(INPUT)
   val debug = new ioDebug
   val pcr_req = (new FIFOIO) { new PCRReq }.flip
-  val pcr_rep = (new PipeIO) { Bits(width = 64) }
+  val pcr_rep = (new FIFOIO) { Bits(width = 64) }
   val ipi = (new FIFOIO) { Bits(width = log2Up(NTILES)) }
 }
 
@@ -220,6 +220,8 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
         my_reset := pcr_wdata(0)
       }
     }
+
+    cpu.pcr_rep.ready := Bool(true)
     when (cpu.pcr_rep.valid) {
       pcr_done := Bool(true)
       rdata := cpu.pcr_rep.bits
diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala
index c97fb265..d255ed5a 100644
--- a/rocket/src/main/scala/top.scala
+++ b/rocket/src/main/scala/top.scala
@@ -107,7 +107,13 @@ class Top extends Component
     val hl = uncore.io.htif(i)
     val tl = uncore.io.tiles(i)
     val tile = new Tile(co, resetSignal = hl.reset)
-    tile.io.host <> hl
+
+    tile.io.host.reset := Reg(Reg(hl.reset))
+    tile.io.host.pcr_req <> Queue(hl.pcr_req)
+    hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
+    hl.ipi <> Queue(tile.io.host.ipi)
+    error_mode = error_mode || Reg(tile.io.host.debug.error_mode)
+
     tl.xact_init <> Queue(tile.io.tilelink.xact_init)
     tl.xact_init_data <> Queue(tile.io.tilelink.xact_init_data)
     tile.io.tilelink.xact_abort <> Queue(tl.xact_abort)
@@ -117,7 +123,6 @@ class Top extends Component
     tl.probe_rep <> Queue(tile.io.tilelink.probe_rep, 1)
     tl.probe_rep_data <> Queue(tile.io.tilelink.probe_rep_data)
     tl.incoherent := hl.reset
-    error_mode = error_mode || tile.io.host.debug.error_mode
   }
   io.debug.error_mode := error_mode
 }