riscv/rocket-chip
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Use Mem instead of Vec[Reg]

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Andrew Waterman 2014-05-18 19:26:35 -07:00
parent 0e39346a12
commit 364a6de214
1 changed files with 1 additions and 1 deletions
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uncore/src/main/scala/htif.scala
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@ -84,7 +84,7 @@ class HTIF(w: Int, pcr_RESET: Int, nSCR: Int, offsetBits: Int)(implicit conf: Ti
val rx_word_count = (rx_count >> UInt(log2Up(short_request_bits/w))) val rx_word_count = (rx_count >> UInt(log2Up(short_request_bits/w)))
val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR
val packet_ram_depth = long_request_bits/short_request_bits-1 val packet_ram_depth = long_request_bits/short_request_bits-1
val packet_ram = Vec.fill(packet_ram_depth){Reg(Bits(width = short_request_bits))} val packet_ram = Mem(Bits(width = short_request_bits), packet_ram_depth)
when (rx_word_done && io.host.in.ready) { when (rx_word_done && io.host.in.ready) {
packet_ram(rx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)) := rx_shifter_in packet_ram(rx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)) := rx_shifter_in
} }