From 364a6de2145dd3e81cd432cf31fa56bb177eef3f Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 18 May 2014 19:26:35 -0700 Subject: [PATCH] Use Mem instead of Vec[Reg] --- uncore/src/main/scala/htif.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uncore/src/main/scala/htif.scala b/uncore/src/main/scala/htif.scala index 41d6df28..cc1c1c62 100644 --- a/uncore/src/main/scala/htif.scala +++ b/uncore/src/main/scala/htif.scala @@ -84,7 +84,7 @@ class HTIF(w: Int, pcr_RESET: Int, nSCR: Int, offsetBits: Int)(implicit conf: Ti val rx_word_count = (rx_count >> UInt(log2Up(short_request_bits/w))) val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR val packet_ram_depth = long_request_bits/short_request_bits-1 - val packet_ram = Vec.fill(packet_ram_depth){Reg(Bits(width = short_request_bits))} + val packet_ram = Mem(Bits(width = short_request_bits), packet_ram_depth) when (rx_word_done && io.host.in.ready) { packet_ram(rx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)) := rx_shifter_in }