riscv/rocket-chip
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Merge 'origin/master' into auto-plusargs

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This commit is contained in:
Schuyler Eldridge 2018-01-16 15:45:53 -05:00
commit 355d3b15e8
2 changed files with 3 additions and 1 deletions
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2
csrc/verilator.h
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@ -12,7 +12,7 @@ class VerilatedVcdFILE : public VerilatedVcdFile {
public: public:
VerilatedVcdFILE(FILE* file) : file(file) {} VerilatedVcdFILE(FILE* file) : file(file) {}
~VerilatedVcdFILE() {} ~VerilatedVcdFILE() {}
bool open(const string& name) override { bool open(const std::string& name) override {
// file should already be open // file should already be open
return file != NULL; return file != NULL;
} }

2
src/main/scala/rocket/BusErrorUnit.scala
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@ -12,6 +12,7 @@ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._ import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._ import freechips.rocketchip.interrupts._
import freechips.rocketchip.util.property._
trait BusErrors extends Bundle { trait BusErrors extends Bundle {
def toErrorList: List[Option[Valid[UInt]]] def toErrorList: List[Option[Valid[UInt]]]
@ -59,6 +60,7 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
cause := i cause := i
value := s.get.bits value := s.get.bits
} }
cover(en, s"BusErrorCause_$i", s"Core;;BusErrorCause $i covered")
} }
} }