92 lines
3.1 KiB
Scala
92 lines
3.1 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.rocket
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import Chisel._
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import Chisel.ImplicitConversions._
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import chisel3.util.Valid
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.util._
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import freechips.rocketchip.tile._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util.property._
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trait BusErrors extends Bundle {
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def toErrorList: List[Option[Valid[UInt]]]
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}
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class L1BusErrors(implicit p: Parameters) extends CoreBundle()(p) with BusErrors {
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val icache = new ICacheErrors
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val dcache = new DCacheErrors
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def toErrorList =
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List(None, None, icache.correctable, icache.uncorrectable,
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None, Some(dcache.bus), dcache.correctable, dcache.uncorrectable)
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}
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case class BusErrorUnitParams(addr: BigInt, size: Int = 4096)
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class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit p: Parameters) extends LazyModule {
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val regWidth = 64
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val device = new SimpleDevice("bus-error-unit", Seq("sifive,buserror0"))
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val intNode = IntSourceNode(IntSourcePortSimple(resources = device.int))
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val node = TLRegisterNode(
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address = Seq(AddressSet(params.addr, params.size-1)),
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device = device,
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beatBytes = p(XLen)/8)
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val errors = t.flip
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val interrupt = Bool().asOutput
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})
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val sources = io.errors.toErrorList
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val cause = Reg(init = UInt(0, log2Ceil(sources.lastIndexWhere(_.nonEmpty) + 1)))
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val value = Reg(UInt(width = sources.flatten.map(_.bits.getWidth).max))
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require(value.getWidth <= regWidth)
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val enable = Reg(init = Vec(sources.map(_.nonEmpty.B)))
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val global_interrupt = Reg(init = Vec.fill(sources.size)(false.B))
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val accrued = Reg(init = Vec.fill(sources.size)(false.B))
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val local_interrupt = Reg(init = Vec.fill(sources.size)(false.B))
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for ((((s, en), acc), i) <- (sources zip enable zip accrued).zipWithIndex; if s.nonEmpty) {
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when (s.get.valid) {
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acc := true
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when (en && cause === 0) {
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cause := i
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value := s.get.bits
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}
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cover(en, s"BusErrorCause_$i", s"Core;;BusErrorCause $i covered")
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}
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}
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val (int_out, _) = intNode.out(0)
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io.interrupt := (accrued.asUInt & local_interrupt.asUInt).orR
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int_out(0) := (accrued.asUInt & global_interrupt.asUInt).orR
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def reg(r: UInt) = RegField.bytes(r, (r.getWidth + 7)/8)
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def reg(v: Vec[Bool]) = v.map(r => RegField(1, r))
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def numberRegs(x: Seq[Seq[RegField]]) = x.zipWithIndex.map { case (f, i) => (i * regWidth / 8) -> f }
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node.regmap(numberRegs(Seq(
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reg(cause),
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reg(value),
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reg(enable),
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reg(global_interrupt),
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reg(accrued),
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reg(local_interrupt))):_*)
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// hardwire mask bits for unsupported sources to 0
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for ((s, i) <- sources.zipWithIndex; if s.isEmpty) {
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enable(i) := false
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global_interrupt(i) := false
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accrued(i) := false
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local_interrupt(i) := false
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}
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}
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}
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