diff --git a/csrc/verilator.h b/csrc/verilator.h
index b4cd0659..d5ada6c0 100644
--- a/csrc/verilator.h
+++ b/csrc/verilator.h
@@ -12,7 +12,7 @@ class VerilatedVcdFILE : public VerilatedVcdFile {
  public:
   VerilatedVcdFILE(FILE* file) : file(file) {}
   ~VerilatedVcdFILE() {}
-  bool open(const string& name) override {
+  bool open(const std::string& name) override {
     // file should already be open
     return file != NULL;
   }
diff --git a/src/main/scala/rocket/BusErrorUnit.scala b/src/main/scala/rocket/BusErrorUnit.scala
index cb922ee2..b9834d70 100644
--- a/src/main/scala/rocket/BusErrorUnit.scala
+++ b/src/main/scala/rocket/BusErrorUnit.scala
@@ -12,6 +12,7 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.interrupts._
+import freechips.rocketchip.util.property._
 
 trait BusErrors extends Bundle {
   def toErrorList: List[Option[Valid[UInt]]]
@@ -59,6 +60,7 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
           cause := i
           value := s.get.bits
         }
+        cover(en, s"BusErrorCause_$i", s"Core;;BusErrorCause $i covered")
       }
     }