From 35506279af7bd3b8377180eb9db8c3dd641dbb58 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 30 Nov 2017 16:38:45 -0800 Subject: [PATCH] regmapper: fix d_ready => d_bits loop in RegField.bytes RegField.bytes updates only those bytes which are written every cycle. However, there was a bug that it would try to return the updated value on reads. This led to another TL-spec violating combinational path, just like the Debug module. --- src/main/scala/regmapper/RegField.scala | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/main/scala/regmapper/RegField.scala b/src/main/scala/regmapper/RegField.scala index 3cf0caa8..16212c24 100644 --- a/src/main/scala/regmapper/RegField.scala +++ b/src/main/scala/regmapper/RegField.scala @@ -113,13 +113,15 @@ object RegField // than the intended bus width of the device (atomic updates are impossible). def bytes(reg: UInt, numBytes: Int): Seq[RegField] = { val pad = reg | UInt(0, width = 8*numBytes) - val bytes = Wire(init = Vec.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) }) + val oldBytes = Vec.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) } + val newBytes = Wire(init = oldBytes) val valids = Wire(init = Vec.fill(numBytes) { Bool(false) }) - when (valids.reduce(_ || _)) { reg := bytes.asUInt } - bytes.zipWithIndex.map { case (b, i) => RegField(8, b, - RegWriteFn((valid, data) => { + when (valids.reduce(_ || _)) { reg := newBytes.asUInt } + Seq.tabulate(numBytes) { i => + RegField(8, oldBytes(i), + RegWriteFn((valid, data) => { valids(i) := valid - when (valid) { bytes(i) := data } + when (valid) { newBytes(i) := data } Bool(true) }))}}