riscv/rocket-chip
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don't repeat external addr map base

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This commit is contained in:
Howard Mao
2016-08-09 21:20:54 -07:00
parent 3ea2f4a6c4
commit 33f13d5c49
2 changed files with 8 additions and 4 deletions
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2
src/main/scala/Configs.scala
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@ -41,7 +41,7 @@ class BaseConfig extends Config (
val memSize = 0x10000000L
val intern = AddrMapEntry("int", internalIOAddrMap)
val extern = AddrMapEntry("ext", MemRange(0x50000000L, 0x30000000L, MemAttr(AddrMapProt.RWX)))
val extern = AddrMapEntry("ext", site(ExtAddrMap).toRange)
val ioMap = if (site(ExportMMIOPort)) AddrMap(intern, extern) else AddrMap(intern)
val addrMap = AddrMap(