From 33f13d5c498bc20c08c209321a6434063c1275f8 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Tue, 9 Aug 2016 21:20:54 -0700
Subject: [PATCH] don't repeat external addr map base

---
 junctions/src/main/scala/addrmap.scala | 10 +++++++---
 src/main/scala/Configs.scala           |  2 +-
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/junctions/src/main/scala/addrmap.scala b/junctions/src/main/scala/addrmap.scala
index b3b1ef61..0424509c 100644
--- a/junctions/src/main/scala/addrmap.scala
+++ b/junctions/src/main/scala/addrmap.scala
@@ -78,15 +78,16 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
   def isEmpty = entries.isEmpty
   def length = entries.size
   def numSlaves = entries.map(_.region.numSlaves).foldLeft(0)(_ + _)
-  def attr = ???
 
   private val slavePorts = HashMap[String, Int]()
   private val mapping = HashMap[String, MemRegion]()
 
-  val (size: BigInt, entries: Seq[AddrMapEntry]) = {
+  val (size: BigInt, entries: Seq[AddrMapEntry], attr: MemAttr) = {
     var ind = 0
     var base = start
     var rebasedEntries = collection.mutable.ArrayBuffer[AddrMapEntry]()
+    var prot = 0
+    var cacheable = true
     for (AddrMapEntry(name, r) <- entriesIn) {
       if (r.start != 0) {
         val align = BigInt(1) << log2Ceil(r.size)
@@ -112,8 +113,10 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
 
       ind += r.numSlaves
       base += r.size
+      prot |= r.attr.prot
+      cacheable &&= r.attr.cacheable
     }
-    (base - start, rebasedEntries)
+    (base - start, rebasedEntries, MemAttr(prot, cacheable))
   }
 
   val flatten: Seq[(String, MemRange)] = {
@@ -123,6 +126,7 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
     arr
   }
 
+  def toRange: MemRange = MemRange(start, size, attr)
   def apply(name: String): MemRegion = mapping(name)
   def contains(name: String): Boolean = mapping.contains(name)
   def port(name: String): Int = slavePorts(name)
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index b55a2a81..f4832b8b 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -41,7 +41,7 @@ class BaseConfig extends Config (
       val memSize = 0x10000000L
 
       val intern = AddrMapEntry("int", internalIOAddrMap)
-      val extern = AddrMapEntry("ext", MemRange(0x50000000L, 0x30000000L, MemAttr(AddrMapProt.RWX)))
+      val extern = AddrMapEntry("ext", site(ExtAddrMap).toRange)
       val ioMap = if (site(ExportMMIOPort)) AddrMap(intern, extern) else AddrMap(intern)
 
       val addrMap = AddrMap(