riscv/rocket-chip
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Chisel3 compatibility fix

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No need for a Vec here.
This commit is contained in:
Andrew Waterman 2016-01-15 15:16:54 -08:00
parent c8fa7c43a9
commit 335fb73120
1 changed files with 3 additions and 2 deletions
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5
junctions/src/main/scala/nasti.scala
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@ -560,10 +560,11 @@ class NastiRecursiveInterconnect(
err_slave.io <> xbarSlave err_slave.io <> xbarSlave
} else { } else {
val subSlaves = submap.countSlaves val subSlaves = submap.countSlaves
val outputs = Vec(io.slaves.drop(slaveInd).take(subSlaves)) val outputs = io.slaves.drop(slaveInd).take(subSlaves)
val ic = Module(new NastiRecursiveInterconnect(1, subSlaves, submap, start)) val ic = Module(new NastiRecursiveInterconnect(1, subSlaves, submap, start))
ic.io.masters.head <> xbarSlave ic.io.masters.head <> xbarSlave
outputs <> ic.io.slaves for ((o, s) <- outputs zip ic.io.slaves)
o <> s
slaveInd += subSlaves slaveInd += subSlaves
} }
case MemChannels(_, nchannels, _) => case MemChannels(_, nchannels, _) =>