From 335fb7312063f04c11a736fa321397f9eca4976c Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Fri, 15 Jan 2016 15:16:54 -0800
Subject: [PATCH] Chisel3 compatibility fix

No need for a Vec here.
---
 junctions/src/main/scala/nasti.scala | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/junctions/src/main/scala/nasti.scala b/junctions/src/main/scala/nasti.scala
index 6624b702..0baa463d 100644
--- a/junctions/src/main/scala/nasti.scala
+++ b/junctions/src/main/scala/nasti.scala
@@ -560,10 +560,11 @@ class NastiRecursiveInterconnect(
             err_slave.io <> xbarSlave
           } else {
             val subSlaves = submap.countSlaves
-            val outputs = Vec(io.slaves.drop(slaveInd).take(subSlaves))
+            val outputs = io.slaves.drop(slaveInd).take(subSlaves)
             val ic = Module(new NastiRecursiveInterconnect(1, subSlaves, submap, start))
             ic.io.masters.head <> xbarSlave
-            outputs <> ic.io.slaves
+            for ((o, s) <- outputs zip ic.io.slaves)
+              o <> s
             slaveInd += subSlaves
           }
         case MemChannels(_, nchannels, _) =>