riscv/rocket-chip
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[fpu] fix rounding mode bug in fdivfsqrt

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Christopher Celio committed 2016-02-08 17:38:31 -08:00
1 parent 5abfd1a4ab
commit 31dd311aff
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rocket/src/main/scala/fpu.scala
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@@ -633,7 +633,7 @@ class FPU(implicit p: Parameters) extends CoreModule()(p) {
val divSqrt_toSingle = Module(new hardfloat.RecFNToRecFN(11, 53, 8, 24)) val divSqrt_toSingle = Module(new hardfloat.RecFNToRecFN(11, 53, 8, 24))
divSqrt_toSingle.io.in := divSqrt_wdata_double divSqrt_toSingle.io.in := divSqrt_wdata_double
divSqrt_toSingle.io.roundingMode := ex_rm divSqrt_toSingle.io.roundingMode := divSqrt_rm
divSqrt_wdata := Mux(divSqrt_single, divSqrt_toSingle.io.out, divSqrt_wdata_double) divSqrt_wdata := Mux(divSqrt_single, divSqrt_toSingle.io.out, divSqrt_wdata_double)
divSqrt_flags := divSqrt_flags_double | Mux(divSqrt_single, divSqrt_toSingle.io.exceptionFlags, Bits(0)) divSqrt_flags := divSqrt_flags_double | Mux(divSqrt_single, divSqrt_toSingle.io.exceptionFlags, Bits(0))
} }