From 31dd311affd4be2e00e83e6f22783081c331e2c6 Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Mon, 8 Feb 2016 17:38:31 -0800 Subject: [PATCH] [fpu] fix rounding mode bug in fdivfsqrt --- rocket/src/main/scala/fpu.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index 77e37e8f..68dea0a4 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -633,7 +633,7 @@ class FPU(implicit p: Parameters) extends CoreModule()(p) { val divSqrt_toSingle = Module(new hardfloat.RecFNToRecFN(11, 53, 8, 24)) divSqrt_toSingle.io.in := divSqrt_wdata_double - divSqrt_toSingle.io.roundingMode := ex_rm + divSqrt_toSingle.io.roundingMode := divSqrt_rm divSqrt_wdata := Mux(divSqrt_single, divSqrt_toSingle.io.out, divSqrt_wdata_double) divSqrt_flags := divSqrt_flags_double | Mux(divSqrt_single, divSqrt_toSingle.io.exceptionFlags, Bits(0)) }