riscv/rocket-chip
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Use Mem for ReorderQueue data

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This might improve FPGA QoR.
This commit is contained in:
Andrew Waterman 2016-05-26 01:02:56 -07:00
parent 1c8745dfd2
commit 2ece3e6102
1 changed files with 1 additions and 1 deletions
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junctions/src/main/scala/util.scala
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@ -182,7 +182,7 @@ class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
val deq = new ReorderDequeueIO(dType, tagWidth) val deq = new ReorderDequeueIO(dType, tagWidth)
} }
val roq_data = Reg(Vec(size, dType.cloneType)) val roq_data = Mem(size, dType.cloneType)
val roq_tags = Reg(Vec(size, UInt(width = tagWidth))) val roq_tags = Reg(Vec(size, UInt(width = tagWidth)))
val roq_free = Reg(init = Vec.fill(size)(Bool(true))) val roq_free = Reg(init = Vec.fill(size)(Bool(true)))