From 2d4e5d3813379537b82765c04dcc5432b8410c65 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Wed, 2 May 2012 19:27:27 -0700
Subject: [PATCH] fix pseudo-LRU verilog generation bug

---
 rocket/src/main/scala/itlb.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/itlb.scala b/rocket/src/main/scala/itlb.scala
index 78f2d886..f8deb5cd 100644
--- a/rocket/src/main/scala/itlb.scala
+++ b/rocket/src/main/scala/itlb.scala
@@ -56,7 +56,7 @@ class PseudoLRU(n: Int)
     var idx = UFix(1,1)
     for (i <- log2up(n)-1 to 0 by -1) {
       val bit = way(i)
-      val mask = (UFix(1) << idx)(n-1,0)
+      val mask = (UFix(1,n) << idx)(n-1,0)
       next_state = next_state & ~mask | Mux(bit, UFix(0), mask)
       //next_state.bitSet(idx, !bit)
       idx = Cat(idx, bit)