riscv/rocket-chip
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pass invalidate_lr through simple cache interface (#45)

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Colin Schmidt 2016-06-09 17:22:36 -07:00 committed by Andrew Waterman
parent 586c1079d0
commit 2c325151bf
1 changed files with 1 additions and 0 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -1133,6 +1133,7 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module
val s2_req_fire = Reg(next=s1_req_fire) val s2_req_fire = Reg(next=s1_req_fire)
val s3_nack = Reg(next=io.cache.s2_nack) val s3_nack = Reg(next=io.cache.s2_nack)
io.cache.invalidate_lr := io.requestor.invalidate_lr
io.cache.req <> req_arb.io.out io.cache.req <> req_arb.io.out
io.cache.req.bits.phys := Bool(true) io.cache.req.bits.phys := Bool(true)
io.cache.s1_kill := io.cache.s2_nack io.cache.s1_kill := io.cache.s2_nack