From 2c325151bfb7f2269afe4155670218fe586396be Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 9 Jun 2016 17:22:36 -0700 Subject: [PATCH] pass invalidate_lr through simple cache interface (#45) --- rocket/src/main/scala/nbdcache.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 87a8179a..bbce5980 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -1133,6 +1133,7 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module val s2_req_fire = Reg(next=s1_req_fire) val s3_nack = Reg(next=io.cache.s2_nack) + io.cache.invalidate_lr := io.requestor.invalidate_lr io.cache.req <> req_arb.io.out io.cache.req.bits.phys := Bool(true) io.cache.s1_kill := io.cache.s2_nack