riscv/rocket-chip
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cleanups supporting uncore hierarchy

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This commit is contained in:
Henry Cook 2014-01-21 12:08:42 -08:00
parent febd26f505
commit 2c2b3a7678
3 changed files with 5 additions and 5 deletions
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2
rocket/src/main/scala/icache.scala
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@ -248,7 +248,7 @@ class ICache(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module
io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout) io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
val finish_q = Module(new Queue(new GrantAck, 1)) val finish_q = Module(new Queue(new GrantAck, 1))
finish_q.io.enq.valid := refill_done && tl.co.requiresAck(io.mem.grant.bits.payload) finish_q.io.enq.valid := refill_done && tl.co.requiresAckForGrant(io.mem.grant.bits.payload.g_type)
finish_q.io.enq.bits.master_xact_id := io.mem.grant.bits.payload.master_xact_id finish_q.io.enq.bits.master_xact_id := io.mem.grant.bits.payload.master_xact_id
// output signals // output signals

6
rocket/src/main/scala/nbdcache.scala
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@ -260,7 +260,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
} }
val ackq = Module(new Queue(new LogicalNetworkIO(new GrantAck), 1)) val ackq = Module(new Queue(new LogicalNetworkIO(new GrantAck), 1))
ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAck(io.mem_grant.bits.payload) ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAckForGrant(io.mem_grant.bits.payload.g_type)
ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id
ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src
val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp
@ -686,12 +686,12 @@ class AMOALU(implicit conf: DCacheConfig) extends Module {
class HellaCacheReq(implicit val conf: DCacheConfig) extends DCacheBundle { class HellaCacheReq(implicit val conf: DCacheConfig) extends DCacheBundle {
val kill = Bool() val kill = Bool()
val typ = Bits(width = 3) val typ = Bits(width = MT_SZ)
val phys = Bool() val phys = Bool()
val addr = UInt(width = conf.maxaddrbits) val addr = UInt(width = conf.maxaddrbits)
val data = Bits(width = conf.databits) val data = Bits(width = conf.databits)
val tag = Bits(width = conf.reqtagbits) val tag = Bits(width = conf.reqtagbits)
val cmd = Bits(width = 4) val cmd = Bits(width = M_SZ)
} }
class HellaCacheResp(implicit val conf: DCacheConfig) extends DCacheBundle { class HellaCacheResp(implicit val conf: DCacheConfig) extends DCacheBundle {

2
rocket/src/main/scala/tile.scala
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@ -20,7 +20,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
if (fastLoadByte) require(fastLoadWord) if (fastLoadByte) require(fastLoadWord)
} }
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) with ClientCoherenceAgent class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal)
{ {
val memPorts = 2 // Number of ports to outer memory system from tile: 1 from I$, 1 from D$ val memPorts = 2 // Number of ports to outer memory system from tile: 1 from I$, 1 from D$
val dcachePortId = 0 val dcachePortId = 0