diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 5a61adb8..88742586 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -248,7 +248,7 @@ class ICache(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module
   io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
 
   val finish_q = Module(new Queue(new GrantAck, 1))
-  finish_q.io.enq.valid := refill_done && tl.co.requiresAck(io.mem.grant.bits.payload)
+  finish_q.io.enq.valid := refill_done && tl.co.requiresAckForGrant(io.mem.grant.bits.payload.g_type)
   finish_q.io.enq.bits.master_xact_id := io.mem.grant.bits.payload.master_xact_id
 
   // output signals
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index ba08110c..7eb5b15d 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -260,7 +260,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
   }
 
   val ackq = Module(new Queue(new LogicalNetworkIO(new GrantAck), 1))
-  ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAck(io.mem_grant.bits.payload)
+  ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAckForGrant(io.mem_grant.bits.payload.g_type)
   ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id
   ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src
   val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp
@@ -686,12 +686,12 @@ class AMOALU(implicit conf: DCacheConfig) extends Module {
 
 class HellaCacheReq(implicit val conf: DCacheConfig) extends DCacheBundle {
   val kill = Bool()
-  val typ  = Bits(width = 3)
+  val typ  = Bits(width = MT_SZ)
   val phys = Bool()
   val addr = UInt(width = conf.maxaddrbits)
   val data = Bits(width = conf.databits)
   val tag  = Bits(width = conf.reqtagbits)
-  val cmd  = Bits(width = 4)
+  val cmd  = Bits(width = M_SZ)
 }
 
 class HellaCacheResp(implicit val conf: DCacheConfig) extends DCacheBundle {
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index a194fbab..840a8c3d 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -20,7 +20,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
   if (fastLoadByte) require(fastLoadWord)
 }
 
-class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) with ClientCoherenceAgent
+class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal)
 {
   val memPorts = 2 // Number of ports to outer memory system from tile: 1 from I$, 1 from D$
   val dcachePortId = 0