riscv/rocket-chip
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cleanups supporting uncore hierarchy

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This commit is contained in:
Henry Cook
2014-01-21 12:08:42 -08:00
parent febd26f505
commit 2c2b3a7678
3 changed files with 5 additions and 5 deletions
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2
rocket/src/main/scala/tile.scala
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@ -20,7 +20,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
if (fastLoadByte) require(fastLoadWord)
}
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) with ClientCoherenceAgent
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal)
{
val memPorts = 2 // Number of ports to outer memory system from tile: 1 from I$, 1 from D$
val dcachePortId = 0