riscv/rocket-chip
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cleanups supporting uncore hierarchy

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This commit is contained in:
Henry Cook
2014-01-21 12:08:42 -08:00
parent febd26f505
commit 2c2b3a7678
3 changed files with 5 additions and 5 deletions
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2
rocket/src/main/scala/icache.scala
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@ -248,7 +248,7 @@ class ICache(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module
io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
val finish_q = Module(new Queue(new GrantAck, 1))
finish_q.io.enq.valid := refill_done && tl.co.requiresAck(io.mem.grant.bits.payload)
finish_q.io.enq.valid := refill_done && tl.co.requiresAckForGrant(io.mem.grant.bits.payload.g_type)
finish_q.io.enq.bits.master_xact_id := io.mem.grant.bits.payload.master_xact_id
// output signals