diff --git a/rocket/src/main/scala/slowio.scala b/rocket/src/main/scala/slowio.scala
new file mode 100644
index 00000000..c1535044
--- /dev/null
+++ b/rocket/src/main/scala/slowio.scala
@@ -0,0 +1,49 @@
+package rocket
+
+import Chisel._
+import Constants._
+
+class slowIO[T <: Data](divisor: Int, hold_cycles: Int)(data: => T) extends Component
+{
+  val io = new Bundle {
+    val out_fast = new ioDecoupled()(data).flip
+    val out_slow = new ioDecoupled()(data)
+
+    val in_fast = new ioDecoupled()(data)
+    val in_slow = new ioDecoupled()(data).flip
+
+    val clk_slow = Bool(OUTPUT)
+  }
+
+  require((divisor & (divisor-1)) == 0)
+  require(hold_cycles < divisor/2 && hold_cycles >= 2)
+
+  val cnt = Reg() { UFix(width = log2up(divisor)) }
+  cnt := cnt + UFix(1)
+  val out_en = cnt === UFix(divisor/2+hold_cycles-1) // rising edge + hold time
+  val in_en = cnt === UFix(divisor/2-1) // rising edge
+
+  val in_slow_rdy = Reg(resetVal = Bool(false))
+  val out_slow_val = Reg(resetVal = Bool(false))
+  val out_slow_bits = Reg() { data }
+
+  val fromhost_q = new queue(1)(data)
+  fromhost_q.io.enq.valid := in_en && io.in_slow.valid && in_slow_rdy
+  fromhost_q.io.enq.bits := io.in_slow.bits
+  fromhost_q.io.deq <> io.in_fast
+
+  val tohost_q = new queue(1)(data)
+  tohost_q.io.enq <> io.out_fast
+  tohost_q.io.deq.ready := in_en && io.out_slow.ready && out_slow_val
+
+  when (out_en) {
+    in_slow_rdy := fromhost_q.io.enq.ready
+    out_slow_val := tohost_q.io.deq.valid
+    out_slow_bits := tohost_q.io.deq.bits
+  }
+
+  io.in_slow.ready := in_slow_rdy
+  io.out_slow.valid := out_slow_val
+  io.out_slow.bits := out_slow_bits
+  io.clk_slow := cnt(log2up(divisor)-1).toBool
+}
diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala
index 6c62a428..dcd394dc 100644
--- a/rocket/src/main/scala/top.scala
+++ b/rocket/src/main/scala/top.scala
@@ -7,6 +7,7 @@ import Constants._;
 class ioTop(htif_width: Int) extends Bundle  {
   val debug   = new ioDebug();
   val host    = new ioHost(htif_width);
+  val host_clk = Bool(OUTPUT)
   val mem     = new ioMem
 }
 
@@ -49,7 +50,14 @@ class Top() extends Component {
     cpu.io.vimem <> vicache.io.cpu;
   }
 
-  htif.io.host <> io.host
+  // pad out the HTIF using a divided clock
+  val slow_io = (new slowIO(64, 16)) { Bits(width = htif_width) }
+  htif.io.host.out <> slow_io.io.out_fast
+  io.host.out <> slow_io.io.out_slow
+  htif.io.host.in <> slow_io.io.in_fast
+  io.host.in <> slow_io.io.in_slow
+  io.host_clk := slow_io.io.clk_slow
+
   cpu.io.host       <> htif.io.cpu(0);
   cpu.io.debug      <> io.debug;