From 288d7169ae032ec0afadf222916e8edd4a568f15 Mon Sep 17 00:00:00 2001
From: Jack Koenig <jack.koenig3@gmail.com>
Date: Sun, 23 Oct 2016 23:07:47 -0700
Subject: [PATCH] Bump firrtl and update vsim Makefrag-verilog (#409)

---
 firrtl                | 2 +-
 vsim/Makefrag-verilog | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/firrtl b/firrtl
index 8b12dcbb..bcf73fb7 160000
--- a/firrtl
+++ b/firrtl
@@ -1 +1 @@
-Subproject commit 8b12dcbb76896a19f95dc4da19b3b8c74c1ddda3
+Subproject commit bcf73fb70969e5629a693c18f1f2ee7b37f14a76
diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index 0f078a21..80df7160 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_src
 
 $(generated_dir)/$(long_name).v $(generated_dir)/$(long_name).conf : $(firrtl) $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
-	$(FIRRTL) -i $< -o $(generated_dir)/$(long_name).v -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
+	$(FIRRTL) -i $< -o $(generated_dir)/$(long_name).v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
 
 $(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
 	cd $(generated_dir) && \