riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Use Vec.fill, not Vec.apply, when making Vec literals

Browse Source
This commit is contained in:
Andrew Waterman 2015-09-25 17:06:24 -07:00
parent 2179cb64ae
commit 20b7a82ab6
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
uncore/src/main/scala/rtc.scala
View File

@ -17,12 +17,12 @@ class RTC(pcr_MTIME: Int) extends Module with HTIFParameters {
val sending_addr = Reg(init = Bool(false)) val sending_addr = Reg(init = Bool(false))
val sending_data = Reg(init = Bool(false)) val sending_data = Reg(init = Bool(false))
val send_acked = Reg(init = Vec(nCores, Bool(true))) val send_acked = Reg(init = Vec.fill(nCores)(Bool(true)))
val coreId = Wire(UInt(width = log2Up(nCores))) val coreId = Wire(UInt(width = log2Up(nCores)))
when (rtc_tick) { when (rtc_tick) {
rtc := rtc + UInt(1) rtc := rtc + UInt(1)
send_acked := Vec(nCores, Bool(false)) send_acked := Vec.fill(nCores)(Bool(false))
sending_addr := Bool(true) sending_addr := Bool(true)
sending_data := Bool(true) sending_data := Bool(true)
} }

2
uncore/src/main/scala/tilelink.scala
View File

@ -1263,7 +1263,7 @@ class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
val roq_data = Reg(Vec(dType.cloneType, size)) val roq_data = Reg(Vec(dType.cloneType, size))
val roq_tags = Reg(Vec(UInt(width = tagWidth), size)) val roq_tags = Reg(Vec(UInt(width = tagWidth), size))
val roq_free = Reg(init = Vec(size, Bool(true))) val roq_free = Reg(init = Vec.fill(size)(Bool(true)))
val roq_enq_addr = PriorityEncoder(roq_free) val roq_enq_addr = PriorityEncoder(roq_free)
val roq_deq_addr = PriorityEncoder(roq_tags.map(_ === io.deq.tag)) val roq_deq_addr = PriorityEncoder(roq_tags.map(_ === io.deq.tag))