From 20b7a82ab68ee20a6212a2a6b02c5a2388e1fa22 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 25 Sep 2015 17:06:24 -0700 Subject: [PATCH] Use Vec.fill, not Vec.apply, when making Vec literals --- uncore/src/main/scala/rtc.scala | 4 ++-- uncore/src/main/scala/tilelink.scala | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/uncore/src/main/scala/rtc.scala b/uncore/src/main/scala/rtc.scala index ade83749..2a32fe88 100644 --- a/uncore/src/main/scala/rtc.scala +++ b/uncore/src/main/scala/rtc.scala @@ -17,12 +17,12 @@ class RTC(pcr_MTIME: Int) extends Module with HTIFParameters { val sending_addr = Reg(init = Bool(false)) val sending_data = Reg(init = Bool(false)) - val send_acked = Reg(init = Vec(nCores, Bool(true))) + val send_acked = Reg(init = Vec.fill(nCores)(Bool(true))) val coreId = Wire(UInt(width = log2Up(nCores))) when (rtc_tick) { rtc := rtc + UInt(1) - send_acked := Vec(nCores, Bool(false)) + send_acked := Vec.fill(nCores)(Bool(false)) sending_addr := Bool(true) sending_data := Bool(true) } diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala index 47e5f5fd..f6dbc54d 100644 --- a/uncore/src/main/scala/tilelink.scala +++ b/uncore/src/main/scala/tilelink.scala @@ -1263,7 +1263,7 @@ class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int) val roq_data = Reg(Vec(dType.cloneType, size)) val roq_tags = Reg(Vec(UInt(width = tagWidth), size)) - val roq_free = Reg(init = Vec(size, Bool(true))) + val roq_free = Reg(init = Vec.fill(size)(Bool(true))) val roq_enq_addr = PriorityEncoder(roq_free) val roq_deq_addr = PriorityEncoder(roq_tags.map(_ === io.deq.tag))