From 1db40687c6e55a3205ec81e6a2ce194ce1ad3e3c Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 18 May 2016 16:46:28 -0700
Subject: [PATCH] ahb: eliminate now-unnecesary non-standard hreadyin

---
 junctions/src/main/scala/hasti.scala | 3 +--
 junctions/src/main/scala/poci.scala  | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/junctions/src/main/scala/hasti.scala b/junctions/src/main/scala/hasti.scala
index cf5a319b..ed35d253 100644
--- a/junctions/src/main/scala/hasti.scala
+++ b/junctions/src/main/scala/hasti.scala
@@ -91,7 +91,6 @@ class HastiSlaveIO(implicit p: Parameters) extends HastiBundle()(p) {
   val hrdata = Bits(OUTPUT, hastiDataBits)
 
   val hsel   = Bool(INPUT)
-  val hreadyin  = Bool(INPUT) // !!! non-standard signal
   val hready = Bool(OUTPUT)
   val hresp  = UInt(OUTPUT, SZ_HRESP)
 }
@@ -323,7 +322,7 @@ class HastiSlaveToMaster(implicit p: Parameters) extends HastiModule()(p) {
     val out = new HastiMasterIO
   }
 
-  io.out.htrans    := Mux(io.in.hsel && io.in.hreadyin, io.in.htrans, HTRANS_IDLE)
+  io.out.htrans    := Mux(io.in.hsel, io.in.htrans, HTRANS_IDLE)
   io.out.hmastlock := io.in.hmastlock
   io.out.haddr     := io.in.haddr
   io.out.hwrite    := io.in.hwrite
diff --git a/junctions/src/main/scala/poci.scala b/junctions/src/main/scala/poci.scala
index b4248fe2..ac089164 100644
--- a/junctions/src/main/scala/poci.scala
+++ b/junctions/src/main/scala/poci.scala
@@ -23,7 +23,7 @@ class HastiToPociBridge(implicit p: Parameters) extends HastiModule()(p) {
 
   val s_idle :: s_setup :: s_access :: Nil = Enum(UInt(), 3)
   val state = Reg(init = s_idle)
-  val transfer = io.in.hsel & io.in.hreadyin & io.in.htrans(1)
+  val transfer = io.in.hsel & io.in.htrans(1)
 
   switch (state) {
     is (s_idle) {