riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2 RegisterRouterTest: stall on both edges

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-09-14 18:18:59 -07:00
parent d35060b881
commit 1c7d7f9d32
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
View File

@ -133,7 +133,7 @@ object RRTestRequest
val ovalid = progress && busy
when (progress) {
busy := Mux(busy, !oready, ivalid)
progress := !oready
progress := Mux(busy, !oready, !ivalid)
} .otherwise {
progress := lfsr(0)
}