From 1c7d7f9d32d0f7183895dafc6b6342f8e064aa71 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 14 Sep 2016 18:18:59 -0700 Subject: [PATCH] tilelink2 RegisterRouterTest: stall on both edges --- src/main/scala/uncore/tilelink2/RegisterRouterTest.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala index cdc9814e..8c226f01 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala @@ -133,7 +133,7 @@ object RRTestRequest val ovalid = progress && busy when (progress) { busy := Mux(busy, !oready, ivalid) - progress := !oready + progress := Mux(busy, !oready, !ivalid) } .otherwise { progress := lfsr(0) }