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tilelink2 RegisterRouterTest: stall on both edges

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Wesley W. Terpstra 2016-09-14 18:18:59 -07:00
parent d35060b881
commit 1c7d7f9d32
1 changed files with 1 additions and 1 deletions
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src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
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@ -133,7 +133,7 @@ object RRTestRequest
val ovalid = progress && busy val ovalid = progress && busy
when (progress) { when (progress) {
busy := Mux(busy, !oready, ivalid) busy := Mux(busy, !oready, ivalid)
progress := !oready progress := Mux(busy, !oready, !ivalid)
} .otherwise { } .otherwise {
progress := lfsr(0) progress := lfsr(0)
} }