From 158cee08af1d689167166becaa40462c2d8a78d9 Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Sun, 22 Sep 2013 03:18:06 -0700 Subject: [PATCH] Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads) --- rocket/src/main/scala/rocc.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala index ac314388..80592c03 100644 --- a/rocket/src/main/scala/rocc.scala +++ b/rocket/src/main/scala/rocc.scala @@ -6,13 +6,13 @@ import uncore._ class RoCCInstruction extends Bundle { - val rd = Bits(width = 5) - val rs1 = Bits(width = 5) - val rs2 = Bits(width = 5) val funct = Bits(width = 7) + val rs2 = Bits(width = 5) + val rs1 = Bits(width = 5) val xd = Bool() val xs1 = Bool() val xs2 = Bool() + val rd = Bits(width = 5) val opcode = Bits(width = 7) }