Reduce outstanding mem accesses for FPGAConfig (to reduce MIFTagBits < 7)

2015-07-30 16:30:00 -07:00 · 2015-07-30 16:30:00 -07:00 · 0c9a7817b6
commit 0c9a7817b6
parent 51c42083d0
1 changed files with 1 additions and 0 deletions
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@ -229,6 +229,7 @@ class ZscaleConfig extends ChiselConfig(new WithZscale ++ new DefaultConfig)

 class FPGAConfig extends ChiselConfig (
  (pname,site,here) => pname match {
+    case NAcquireTransactors => 4
    case UseBackupMemoryPort => false
  }
 )